ISL6269 Datasheet, PDF (7/14 Pages) Intersil Corporation – High-Performance Notebook PWM Controller with Audio-Frequency Clamp

ISL6269
LG (Pin 11)
The LG pin is the output of the low-side MOSFET gate
driver. Connect to the gate of the low-side MOSFET.
PVCC (Pin 12)
The PVCC pin is the input voltage bias for the LG low-side
MOSFET gate driver. Connect +5V from the PVCC pin to the
PGND pin. Decouple with at least 1µF of an MLCC capacitor
across the PVCC and PGND pins. The VCC output may be
used for the PVCC input voltage source.
BOOT (Pin 13)
The BOOT pin stores the input voltage for the UG high-side
MOSFET gate driver. Connect an MLCC capacitor across
the BOOT and PHASE pins. The boot capacitor is charged
through an internal boot diode connected from the PVCC pin
to the BOOT pin, each time the PHASE pin drops below
PVCC minus the voltage dropped across the internal boot
diode.
UG (Pin 14)
The UG pin is the output of the high-side MOSFET gate
driver. Connect to the gate of the high-side MOSFET.
PHASE (Pin 15)
The PHASE pin detects the voltage polarity of the PHASE
node and is also the current return path for the UG high-side
MOSFET gate driver. Connect the PHASE pin to the node
consisting of the high-side MOSFET source, the low-side
MOSFET drain, and the output inductor.
PGOOD (Pin 16)
The PGOOD pin is an open-drain output that indicates when
the converter is able to supply regulated voltage. Connect
the PGOOD pin to +5V through a pull-up resistor.
GND (Bottom Pad)
Signal common of the IC. Unless otherwise stated, signals
are referenced to the GND pin, not the PGND pin.
Theory of Operation
Modulator
The ISL6269 is a hybrid of fixed frequency PWM control, and
variable frequency hysteretic control. Intersil’s R³ technology
can simultaneously affect the PWM switching frequency and
PWM duty cycle in response to input voltage and output load
transients. The term “Ripple” in the name “Robust-Ripple-
Regulator” refers to the converter output inductor ripple
current, not the converter output ripple voltage. The R³
modulator synthesizes an AC signal V_R, which is an ideal
representation of the output inductor ripple current. The
duty-cycle of V_R is the result of charge and discharge
current through a ripple capacitor C_R. The current through
C_R is provided by a transconductance amplifier g_m that
measures the VIN and VO pin voltages. The positive slope
of V_R can be written as:
V_RPOS = (g_m) • (V_IN – V_OUT)
(EQ. 1)
The negative slope of V_R can be written as:
V_RNEG = g_m ⋅ V_OUT
(EQ. 2)
Where g_m is the gain of the transconductance amplifier.
A window voltage V_W is referenced with respect to the error
amplifier output voltage V_COMP, creating an envelope into
which the ripple voltage V_R is compared. The amplitude of
V_W is set by a resistor connected across the FSET and GND
pins. The V_R, V_COMP, and V_W signals feed into a window
comparator in which V_COMP is the lower threshold voltage
and V_W is the higher threshold voltage. Figure 3 shows
PWM pulses being generated as V_R traverses the V_W and
V_COMP thresholds . The PWM switching frequency is
proportional to the slew rates of the positive and negative
slopes of V_R; the PWM switching frequency is inversely
proportional to the voltage between V_W and V_COMP.
Ripple Capacitor Voltage CR
Window Voltage VW
Error Amplifier Voltage VCOMP
PWM
FIGURE 3. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
EN, LDO, and POR
The VCC LDO regulates by pulling up towards the voltage at
the VIN pin; the LDO has no pull-down capability. The LDO
is enabled when the EN pin surpasses the rising EN threshold
voltage V_ENTHR. The ISL6269 is enabled once V_VCC has
increased above the rising power-on reset (POR) V_{VCC_THR}
threshold voltage. The controller immediately stops
generating PWM and disables the LDO when the EN pin is
pulled below the falling EN threshold voltage V_ENTHF . The IC
completely shuts off when V_VCC decreases below the falling
POR V_{VCC_THF} threshold voltage.
Soft-Start, and PGOOD
The ISL6269 uses a digital soft-start circuit to ramp the
output voltage of the converter to the programmed regulation
setpoint at a predictable slew rate. The slew rate of the
soft-start sequence has been selected to limit the inrush
current through the output capacitors as they charge to the
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FN9177.3
June 25, 2009