ISL6146AFUZ-TK Datasheet, PDF (7/28 Pages) Intersil Corporation – Low Voltage OR-ing FET Controller

ISL6146
Electrical Specifications V_CC = BIAS = 12V, unless otherwise stated. T_A = +25°C to +85°C. Boldface limits apply over the operating
temperature range, -40°C to +125°C. (Continued)
SYMBOL
PARAMETERS
TEST CONDITIONS
MIN
(Note 8) TYP
MAX
(Note 8) UNITS
t_toffs
I_ON
Slow Turn-off Time
Turn-On Current
V_IN = V_BIAS = 12V, V_GATE = 18V to 10V,
C_GATE = 57nF
BIAS = 12V, VG = 0V
BIAS = 12V, VG = 20V
58
80
µs
1
mA
0.15
mA
V_{VG_FLTr} GATE to V_IN Rising Fault Voltage
GATE > V_IN, enabled, FLT output is high.
320
440
(Does not apply to ISL6146D and ISL6146E)
560
mV
V_{VG_FLTf} GATE to V_IN Falling Fault Voltage
GATE > V_IN, enabled, FLT output is low.
140
220
(Does not apply to ISL6146D and ISL6146E)
300
mV
CONTROL AND REGULATION I/O
V_Rr
Reverse Voltage Detection
Rising V_OUT Threshold
V_OUT rising
V_Rf
Reverse Voltage Detection
Falling V_OUT Threshold
V_OUT falling
t_Rs
Reverse Voltage Detection Response
Time
35
57
10
30
10
79
mV
51
mV
µs
V_{FWD_VR} Amplifier Forward Voltage Regulation ISL6146 controls voltage across FET V_DS to
11
19
V_{FWD_VR} during static forward operation at loads
resulting in Id*r_DS(ON) < V_{FWD_VR}
V_{OS_HS}
HS Comparator Input Offset Voltage
-14
0.7
V_TH(HS5k) ADJ Adjust Threshold with 5k to GND R_ADJ = 5kΩ to GND
0.57
0.8
V_TH(HS100k) ADJ Adjust Threshold with 100k to GND R_ADJ = 100kΩ to GND
10
40
t_HSpd
HS Comparator Response Time
V_OUT > V_IN, 1ns transition, 5V differential
170
V_{FWD_FLT} V_IN to V_OUT Forward Fault Voltage
V_IN > V_OUT, GATE is fully on, FLT output is low
330
450
V_{FWD_FLT_HYS} V_IN to V_OUT Forward Fault Voltage
V_IN > V_OUT, GATE is fully on, FLT output is high
44
Hysteresis
28
mV
14
mV
1.1
V
95
mV
ns
570
mV
mV
FAULT OUTPUT
I_{FLT_SINK} FAULT Sink Current
I_{FLT_LEAK} FAULT Leakage Current
t_{FLT_L2H} FAULT Low to High Delay
t_{FLT_H2L} FAULT High to Low Delay
ENABLE UVLO/OVP/ADJ INPUTS
BIAS = 18V FAULT = 0.5V, V_IN < V_OUT, V_GATE = V_GL 5
FAULT = “V_{FLT_H}”, V_IN > V_OUT, V_GATE = V_IN + V_GQP
GATE = V_GQP to FAULT output is high
GATE = V_IN to FAULT output is low
9
0.04
10
1.7
mA
10
µA
23
µs
3
µs
VthRa
ISL6146A/D EN Rising Vth
580
606
631
mV
VthR_hysa ISL6146A/D EN Vth Hysteresis
-90
mV
VthFb
ISL6146B/E EN Falling Vth
580
606
631
mV
VthF_hysb ISL6146B/E EN Vth Hysteresis
+90
mV
VthFc
ISL6146C OVP Falling Vth
580
606
631
mV
VthF_hysc ISL6146C OVP Vth Hysteresis
+90
mV
VthRc
ISL6146C UVLO Rising Vth
580
606
631
mV
VthR_hysc ISL6146C UVLO Vth Hysteresis
-90
mV
t_EN2GTER
EN/UVLO Rising to GATE Rising Delay
EN/OVP Falling to GATE Rising Delay
10
12
µs
9
12
µs
7
FN7667.4
April 26, 2013