ISL54054_0709 Datasheet, PDF (7/12 Pages) Intersil Corporation – Ultra Low ON-Resistance, Low Voltage, Single Supply, Single SPST/1:2 Distribution Analog Switch

ISL54054, ISL54055
Test Circuits and Waveforms (Continued)
V+
C
NO OR NC
IMPEDANCE
ANALYZER
IN V_INL OR V_INH
COM
GND
FIGURE 5. CAPACITANCE TEST CIRCUIT
Detailed Description
The Intersil ISL54054 and ISL54055 devices consist of low
ON-resistance, low voltage, bi-directional analog switches
designed to operate from a single +1.8V to +5.5V supply.
With a single supply of 5V the typical ON-resistance is only
0.34Ω, with a typical turn-on and turn-off time of: t_ON = 12ns,
t_OFF = 12ns. The devices are especially well suited for
portable battery powered equipment due to its low operating
supply voltage (1.8V), low power consumption (5.5μW), low
leakage currents (300nA max) and the tiny μTDFN package.
These devices have an unique architecture. They have two
signal pins (pin 1 and pin 3) that are simultaneously
connected or disconnected to a single common pin (pin 4)
under the control of a single logic control pin (pin 6). The
ISL54054 switches are OFF when the logic is low and ON
when the logic is high. The ISL54055 are ON when the logic
is low and OFF when the logic is high. This architecture
allows these devices to be used as a single SPST switch or
as a distribution switch to distribute a single source to two
different loads.
SPST operation is achieved by using one of the Nx signal
pins while floating the other Nx signal pin or by externally
connecting the two Nx signal pins together. When both
signal pins are tied together, the r_ON of the SPST is reduced
by half, from 1Ω to 0.5Ω (when operated with a 5V supply).
The ISL54054 is a normally open (NO) SPST analog switch.
The ISL54055 is a normally closed (NC) SPST analog
switch.
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents,
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 6). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND. If these
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (see Figure 6). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low r_ON switch. Connecting schottky
diodes to the signal pins (as shown in Figure 6) will shunt the
fault current to the supply or to ground, thereby protecting
the switch. These schottky diodes must be sized to handle
the expected fault current.
OPTIONAL
SCHOTTKY
DIODE
OPTIONAL
PROTECTION
RESISTOR
V+
IN_X
V_NX
V_COM
OPTIONAL
SCHOTTKY
DIODE
GND
FIGURE 6. OVERVOLTAGE PROTECTION
7
FN6461.1
September 25, 2007