ISL35111_10 Datasheet, PDF (7/9 Pages) Intersil Corporation – 11.1Gb/s Driver

ISL35111
Application Information
Typical application schematic for ISL35111 is shown in Figure 8.
DT
LOS (output)
INPUT SIGNAL
TDSBL
1.2V
1.2V
100nF
1
VDD
2 _{IN_P}
VDD ¹²
OUT_P ¹¹
100nF
3 _{IN_N}
4 _TDSBL
ISL35111
OUT_N ¹⁰
VDD ⁹
1.2V
100nF
100nF
47nF
100pF
OUTPUT SIGNAL
DEA
DEB
NOTES:
12. See “Adjustable De-Emphasis” on page 6 for information on how to connect the DE pins
13. See “Line Silence/Quiescent Mode” on page 6 for details on DT pin operation.
14. Although the filtering network is shown only for one V_DD pin for simplicity, all the V_DD pins need to be connected in this way.
FIGURE 8. TYPICAL APPLICATION REFERENCE SCHEMATIC FOR ISL35111
PCB Layout Considerations
Because of the high speed of the ISL35111 signals,
careful PCB layout is critical to maximize performance.
The following guidelines should be adhered to as closely
as possible:
• All high speed differential pair traces should have a
characteristic impedance of 50Ω with respect to
ground plane and 100Ω with respect to each other.
• Avoid using vias for high speed traces as this will
create discontinuity in the traces characteristic
impedance.
• Input and output traces need to have DC blocking
capacitors (100nF). Capacitors should be placed as
close to the chip as possible.
• For each differential pair, the positive trace and the
negative trace need to be of same length in order to
avoid intra-pair skew. Serpentine technique may be
used to match trace lengths.
• Maintain a constant solid ground plane underneath
the high-speed differential traces
• Each V_DD pin should be connected to 1.2V and also
bypassed to ground through a 47nF and a 100pF
capacitor in parallel. Minimize the trace length and
avoid vias between the V_DD pin and the bypass
capacitors in order to maximize the power supply
noise rejection.
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7
FN6975.1
January 27, 2010