ISL3179E_15 Datasheet, PDF (7/18 Pages) Intersil Corporation – High ESD Protected, +125°C, 40Mbps, 3.3V, Full Fail-Safe, RS-485/RS-422 Transceivers

ISL3179E, ISL3180E
Electrical Specifications Test Conditions: V_CC = 3.0V to 3.6V; Typicals are at V_CC = 3.3V, T_A = +25°C. Boldface limits apply across the
operating temperature range. (Note 7) (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Note 17) TYP (Note 17) UNIT
Receiver Skew | t_PLH - t_PHL |
Receiver Enable to Output High
t_SKD
t_ZH
Figure 8
R_L = 1kΩ, C_L = 15pF, SW = GND (Figure 9),
(Note 11)
Full
-
0
1.5
ns
Full
-
10
15
ns
Receiver Enable to Output Low
t_ZL R_L = 1kΩ, C_L = 15pF, SW = V_CC (Figure 9),
(Note 11)
Full
-
11
15
ns
Receiver Disable from Output High
Receiver Disable from Output Low
Time to Shutdown
Receiver Enable from Shutdown to
Output High
t_HZ R_L = 1kΩ, C_L = 15pF, SW = GND (Figure 9)
t_LZ R_L = 1kΩ, C_L = 15pF, SW = V_CC (Figure 9)
t_SHDN (Note 12)
t_ZH(SHDN) R_L = 1kΩ, C_L = 15pF, SW = GND (Figure 9),
(Notes 12, 14)
Full
-
10
15
ns
Full
-
10
15
ns
Full
60
-
600
ns
Full
-
-
1000
ns
Receiver Enable from Shutdown to t_ZL(SHDN) R_L = 1kΩ, C_L = 15pF, SW = V_CC (Figure 9),
Output Low
(Notes 12, 14)
Full
-
-
1000
ns
NOTES:
7. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise
specified.
8. Supply current specification is valid for loaded drivers when DE = 0V.
9. Applies to peak current. See “Typical Performance Curves” on page 9 for more information.
10. Because of the shutdown feature, keep RE = 0 to prevent the device from entering SHDN.
11. Because of the shutdown feature, the RE signal high time must be short enough (typically <100ns) to prevent the device from entering SHDN.
12. These IC’s are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 60ns, the parts are guaranteed not to
enter shutdown. If the inputs are in this state for at least 700ns, the parts are guaranteed to have entered shutdown. See “Low Power Shutdown
Mode” on page 13.
13. Keep RE = V_CC, and set the DE signal low time >700ns to ensure that the device enters SHDN.
14. Set the RE signal high time >700ns to ensure that the device enters SHDN.
15. This is the part-to-part skew between any two units tested with identical test conditions (Temperature, V_CC, etc.).
16. V_CC = 3.3V ±5%
17. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Test Circuits and Waveforms
V_CC ^DE
DI
Z
D
Y
V_OD
R_L/2
R_L/2 VOC
V_CC ^DE
DI
Z
D
Y
V_OD
375Ω
R_L = 60Ω
V_CM
-7V TO +12V
375Ω
FIGURE 4A. V_OD AND V_OC
FIGURE 4B. V_OD WITH COMMON-MODE LOAD
FIGURE 4. DC DRIVER TEST CIRCUITS
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7
FN6365.5
August 25, 2015