ISL29011 Datasheet, PDF (7/15 Pages) Intersil Corporation – Digital Ambient Light Sensor and Proximity Sensor with Interrupt Function

ISL29011
I²C DATA
I²C SDA IN
I²C SDA OUT
I²C CLK IN
START
DEVICE ADDRESS
W A REGISTER ADDRESS
A
FUNCTIONS
A STOP
A6 A5 A4 A3 A2 A1 A0 W A R7 R6 R5 R4 R3 R2 R1 R0 A B7 B6 B5 B4 B3 B2 B1 B0 A
SDA DRIVEN BY MASTER
A
SDA DRIVEN BY MASTER
A
SDA DRIVEN BY MASTER
A
1 234 5 67 8 9 1234 56 7 8 9 12 345 67 89
FIGURE 2. I²C WRITE TIMING DIAGRAM SAMPLE
Register Set
There are eight registers that are available in the ISL29011. Table 1 summarizes their functions.
ADDR
00h
01h
02h
03h
04h
05h
06h
07h
REG NAME
COMMANDI
COMMANDII
DATA_LSB
DATA_MSB
INT_LT_LSB
INT_LT_MSB
INT_HT_LSB
INT_HT_MSB
7
OP2
Scheme
D7
D15
TL7
TL15
TH7
TH15
6
OP1
FREQ
D6
D14
TL6
TL14
TH6
TH14
TABLE 1. REGISTER SET
BIT
5
4
3
OP0
0
0
IS1
IS0
RES1
D5
D4
D3
D13
D12
D11
TL5
TL4
TL3
TL13
TL12
TL11
TH5
TH4
TH3
TH13
TH12
TH11
2
FLAG
RES0
D2
D10
TL2
TL10
TH2
TH10
1
PRST1
RANGE1
D1
D9
TL1
TL9
TH1
TH9
0
PRST0
RANGE0
D0
D8
TL0
TL8
TH0
TH8
DEFAULT
00h
00h
00h
00h
00h
00h
FFh
FFh
Command Register I 00(hex)
The first command register has the following functions:
1. Operation Mode: Bits 7, 6, and 5.These three bits
determines the operation mode of the device.
TABLE 2. OPERATION MODE
BITS 7 TO 5
OPERATION
000
Power-down the device
001
ALS once
010
IR once
011
Proximity once
100
Reserved (Do not use)
101
ALS continuous
110
IR continuous
111
Proximity continuous
2. Interrupt flag; Bit 2. This is the status bit of the interrupt.
The bit is set to logic high when the interrupt thresholds
have been triggered, and logic low when not yet triggered.
Once triggered, INT pin stays low and the status bit stays
high. Both interrupt pin and the status bit are automatically
cleared at the end of Command Register I transfer.
TABLE 3. INTERRUPT FLAG
BIT 2
OPERATION
0
Interrupt is cleared or not triggered yet
1
Interrupt is triggered
3. Interrupt persist; Bits 1 and 0. The interrupt pin and the
interrupt flag is triggered/set when the data sensor
reading is out of the interrupt threshold window after m
consecutive number of integration cycles. The interrupt
persist bits determine m.
TABLE 4. INTERRUPT PERSIST
BITS 1 TO 0
NUMBER OF INTEGRATION CYCLES
00
1
01
4
10
8
11
16
7
FN6467.2
May 14, 2009