ISL24010 Datasheet, PDF (7/9 Pages) Intersil Corporation – High Voltage TFT-LCD Logic Driver

ISL24010
Typical Performance Curves T_A = 25°C, Output load parallel RC (RL = 5kΩ, CL = 100pF) unless otherwise specified. (Continued)
0
100pF
Pulse Input
1500pF
0
V_ON1 & ₂ = 22V
V_OFF = -5V
50kHz 50% Duty Cycle
2µs/DIV
FIGURE 13. TRANSIENT RESPONSE vs LOAD CAPACITANCE
Application Information
General
The ISL24010 is an Octal voltage level shifter. The part was
designed to level shifts a digital input signal to +22V and -5V
for TFT-LCD displays. The device is capable of level shifting
a CMOS logic signal between +40V and -20V.
Power Supply Decoupling
The ISL24010 requires a 0.1µF decoupling capacitor as
close to the V_ON1, V_ON2 and V_OFF power supply pins for a
large load equal to 5kΩ in parallel with 100pF (Figure 16).
This will deduce any dv/dt between the different supplies and
prevent the internal ESD clamp from turning on and
damaging the part.
Power Supply Sequence
The ISL24010 requires that V_ON2 be greater than or equal to
V_ON1 at all times. Therefore, if V_ON1 and Von 2 are different
supplies, then V_ON2 needs to be turned on before V_ON1.
The reason for this requirement is shown in Circuit 4 in the
Pin Description Table. The ESD protection diode between
V_ON2 and Von 1 will forward bias if V_ON1 becomes a diode
drop greater than V_ON2. Recommended power supply
sequence: V_ON2, V_ON1, V_OFF then input logic signals.
The ESD protection scheme is based on diodes from the
pins to the V_ON2 supply and a dV/dt- triggered clamp. This
dV/dt triggered clamp imposes a maximum supply turn-on
slew rate of 10V/µs. This clamp will trigger if the supply
powers up too fast, causing amps of current to flow. Ground
and V_ON1 are treated as I/O pins with this protection
scheme. In applications where the dV/dt supply ramp could
exceed 10V/µs, such as hot plugging, additional methods
should be employed to ensure the rate of rise is not
exceeded.
Latch-up Proof
The ISL24010 is manufactured in a high voltage DI process
that isolates every transistor in it’s own tub making the part
latch-up proof.
Input Pin Connections
Unused inputs must be tied to ground. Failure to tie unused
input pins to ground will result in a rail to rail oscillations on
the respective output pins and higher unwanted power
dissipation in the part. Under these conditions, the
temperature of the part could get very hot.
Limiting the Output Current
No output short circuit current limit exists on this part. All
applications need to limit the output current to less than
80mA. Adequate thermal heat sinking of the parts is also
required.
Application Diagram (TV)
1.0µF
1.0µF
DC/DC
CONVERTER
V_ON1
V_OFF
V_ON2
1.0µF
TIMING
CON-
TROLLER
ISL24010
LEVEL
SHIFTER
LCD PANEL
FIGURE 14. TYPICAL TV APPLICATION CIRCUIT
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