ISL23428_15 Datasheet, PDF (7/21 Pages) Intersil Corporation – Dual, 128-Tap, Low Voltage Digitally Controlled Potentiometer (XDCP™)

ISL23428
Operating Specifications V_CC = 2.7V to 5.5V, V_LOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated.
Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 19)
TYP
MAX
(Note 7) (Note 19) UNITS
t_DCP Wiper Response Time
W option; CS rising edge to wiper new
0.4
µs
position, from 10% to 90% of final value.
U option; CS rising edge to wiper new
1.5
µs
position, from 10% to 90% of final value.
T option; CS rising edge to wiper new
3.5
µs
position, from 10% to 90% of final value.
tShdnRec DCP Recall Time from Shutdown Mode CS rising edge to wiper recalled position
1.5
µs
and RH connection
V_CC, V_LOGIC V_{CC ,}V_LOGIC Ramp Rate (Note 20)
Ramp
Ramp monotonic at any level
0.01
50
V/ms
Serial Interface Specification For SCK, SDI, SDO, CS Unless Otherwise Noted.
SYMBOL
V_IL
V_IH
Hysteresis
V_OL
R_pu
C_pin
f_SCK
t_CYC
t_WH
t_WL
t_LEAD
t_LAG
t_SU
t_H
t_RI
t_FI
t_DIS
t_SO
t_V
t_HO
PARAMETER
TEST CONDITIONS
Input LOW Voltage
Input HIGH Voltage
SDI and SCK Input Buffer
Hysteresis
V_LOGIC > 2V
V_LOGIC < 2V
SDO Output Buffer LOW Voltage I_OL = 3mA, V_LOGIC > 2V
I_OL = 1.5mA, V_LOGIC < 2V
SDO Pull-Up Resistor Off-Chip
Maximum is determined by
t_RO and t_FO with maximum
bus load Cb = 30pF,
f_SCK = 5MHz
SCK, SDO, SDI, CS Pin Capacitance
SCK Frequency
SPI Clock Cycle Time
SPI Clock High Time
SPI Clock Low Time
Lead Time
Lag Time
SDI, SCK and CS Input Setup Time
SDI, SCK and CS Input Hold Time
SDI, SCK and CS Input Rise Time
SDI, SCK and CS Input Fall Time
SDO Output Disable Time
SDO Output Setup Time
SDO Output Valid Time
SDO Output Hold Time
V_LOGIC = 1.7V to 5.5V
V_LOGIC = 1.2V to 1.6V
V_LOGIC ≥ 1.7V
V_LOGIC ≥ 1.7V
V_LOGIC ≥ 1.7V
V_LOGIC ≥ 1.7V
V_LOGIC ≥ 1.7V
V_LOGIC ≥ 1.7V
V_LOGIC ≥ 1.7V
V_LOGIC ≥ 1.7V
V_LOGIC ≥ 1.7V
V_LOGIC ≥ 1.7V
V_LOGIC ≥ 1.7V
V_LOGIC ≥ 1.7V
V_LOGIC ≥ 1.7V
MIN
(Note 19)
-0.3
0.7 x V_LOGIC
0.05 x V_LOGIC
0.1 x V_LOGIC
0
200
100
100
250
250
50
50
10
10
0
50
150
0
TYP
(Note 7)
10
MAX
(Note 19)
0.3 x V_LOGIC
V_LOGIC+ 0.3
0.4
0.2 x V_LOGIC
1.5
5
1
20
100
UNITS
V
V
V
V
V
V
kΩ
pF
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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7
FN7904.2
September 23, 2015