HIP6020A_01 Datasheet, PDF(7/16 Page) Intersil Corporation – Advanced Dual PWM and Dual Linear Power Controller

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HIP6020A_01 Datasheet, PDF (7/16 Pages) Intersil Corporation – Advanced Dual PWM and Dual Linear Power Controller

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HIP6020A

to 1.5V, while a high input turns Q3 on continuously,

providing a DC current path from the input (+3.3V) to the

output (VOUT2) of the AGP controller.

DRIVE3 (Pin 18)

Connect this pin to the gate of an external MOSFET. This pin

provides the drive for the 1.5V regulatorâs pass transistor.

FB3 (Pin 19)

Connect this pin to the output of the 1.5V linear regulator.

This pin is monitored for undervoltage events.

DRIVE4 (Pin 15)

Connect this pin to the gate of an external MOSFET. This pin

provides the drive for the 1.8V regulatorâs pass transistor.

FB4 (Pin 14)

Connect this pin to the output of the linear 1.8V regulator.

This pin is monitored for undervoltage events.

Description

Operation

The HIP6020A monitors and precisely controls 4 output voltage

levels (Refer to Block, Power System, and Typical Application

Diagrams). It is designed for microprocessor computer

applications with 3.3V, 5V, and 12V bias input from an ATX

power supply. The IC has 2 PWM and two linear controllers.

The first PWM controller (PWM1) is designed to regulate the

microprocessor core voltage (VOUT1). PWM1 controller drives

2 MOSFETs (Q1 and Q2) in a synchronous-rectified buck

converter and regulates the core voltage to a level programmed

by the 5-bit digital-to-analog converter (DAC). The second

PWM controller (PWM2) is designed to regulate the advanced

graphics port (AGP) bus voltage (VOUT2). PWM2 controller

drives a MOSFET (Q3) in a standard buck converter and

regulates the output voltage to a level of 1.5V or fully on to

output 3.3V. Selection of either output voltage is achieved by

applying the proper logic level at the SELECT pin. The two

linear controllers supply the 1.5V GTL bus power (VOUT3) and

the 1.8V memory power (VOUT4).

Initialization

The HIP6020A automatically initializes upon receipt of input

power. Special sequencing of the input supplies is not

necessary. The Power-On Reset (POR) function continually

monitors the input supply voltages. The POR monitors the

bias voltage (+12VIN) at the VCC pin, the 5V input voltage

(+5VIN) on the OCSET1 pin, and the 3.3V input voltage

(+3.3VIN) at the VAUX pin. The normal level on OCSET1 is

equal to +5VIN less a fixed voltage drop (see over-current

protection). The POR function initiates soft-start operation

after all supply voltages exceed their POR thresholds.

Soft-Start

The POR function initiates the soft-start sequence. Initially, the

voltage on the SS pin rapidly increases to approximately 1V

(this minimizes the soft-start interval). Then an internal 28ÂµA

current source charges an external capacitor (CSS) on the SS

pin to 4.5V. The PWM error amplifiers reference inputs

(+ terminal) and outputs (COMP1 pin) are clamped to a level

proportional to the SS pin voltage. As the SS pin voltage slews

from 1V to 4V, the output clamp allows generation of PHASE

pulses of increasing width that charge the output capacitor(s).

After the output voltage increases to approximately 70% of the

set value, the reference input clamp slows the output voltage

rate-of-rise and provides a smooth transition to the final set

voltage. Additionally both linear regulatorsâ reference inputs are

clamped to a voltage proportional to the SS pin voltage. This

method provides a rapid and controlled output voltage rise.

Figure 3 shows the soft-start sequence for the typical

application. At T0 the SS voltage rapidly increases to

approximately 1V. At T1, the SS pin and error amplifier

output voltage reach the valley of the oscillatorâs triangle

wave. The oscillatorâs triangular wave form is compared to

the clamped error amplifier output voltage. As the SS pin

voltage increases, the pulse-width on the PHASE pin

increases. The interval of increasing pulse-width continues

until each PWM output reaches sufficient voltage to transfer

control to the error amplifier input reference clamp. If we

consider the core output (VOUT1) in Figure 3, this time

occurs at T2. During the interval between T2 and T3, the

error amplifier reference ramps to the final value and the

converter regulates the output a voltage proportional to the

SS pin voltage. At T3 the input clamp voltage exceeds the

reference voltage and the output voltage is in regulation.

PGOOD

SOFT-START

(1V/DIV)

OUTPUT

VOLTAGES

(0.5V/DIV)

VOUT2 (= 3.3V)

VOUT1 (DAC = 2.5V)

VOUT4 (= 1.8V)

VOUT3 (= 1.5V)

T0 T1

TIME

FIGURE 3. SOFT-START INTERVAL

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