HIP6003 Datasheet, PDF (7/12 Pages) Intersil Corporation – Buck Pulse-Width Modulator (PWM) Controller and Output Voltage Monitor

HIP6003
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to
another can generate voltage transients across the
impedances of the interconnecting bond wires and circuit
traces. These interconnecting impedances should be
minimized by using wide, short printed circuit traces. The
critical components should be located as close together as
possible using ground plane construction or single point
grounding.
V_IN
HIP6003
UGATE
PHASE
Q1
L_O
V_OUT
C_IN
D2
CO
construction for the circuits shown. Minimize any leakage
current paths on the SS PIN and locate the capacitor, C_SS
close to the SS pin because the internal current source is
only 10µA. Provide local V_CC decoupling between VCC and
GND pins. Locate the capacitor, C_BOOT as close as practical
to the BOOT and PHASE pins.
Feedback Compensation
OSC
V_IN
DRIVER
PWM
COMPARATOR
LO
-
∆V_OSC
+
PHASE
CO
V_OUT
Z_FB
V_E/A
-
Z_IN
+
ERROR ^REFERENCE
AMP
ESR
(PARASITIC)
RETURN
FIGURE 6. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
Figure 6 shows the critical power components of the
converter. To minimize the voltage overshoot the
interconnecting wires indicated by heavy lines should be
part of ground or power plane in a printed circuit board. The
components shown in Figure 6 should be located as close
together as possible. Please note that the capacitors C_IN
and C_O each represent numerous physical capacitors.
Locate the HIP6003 within 3 inches of the MOSFET, Q1.
The circuit traces for the MOSFETs gate and source
connections from the HIP6003 must be sized to handle up to
1A peak current.
BOOT
D1
C_BOOT
+V_IN
Q1 _LO
HIP6003 ^PHASE
V_CC
SS
+12V
D2 CO
V_OUT
C_SS
GND
C_VCC
FIGURE 7. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Figure 7 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
7
DETAILED COMPENSATION COMPONENTS
C2
C1 _R2
Z_FB
V_OUT
Z_IN
C3 _R3
R1
COMP
FB
-
+
HIP6003
DACOUT
FIGURE 8. VOLTAGE - MODE BUCK CONVERTER
COMPENSATION DESIGN
Figure 8 highlights the voltage-mode control loop for a buck
converter. The output voltage (V_OUT) is regulated to the
Reference voltage level. The error amplifier (Error Amp)
output (V_E/A) is compared with the oscillator (OSC)
triangular wave to provide a pulse-width modulated (PWM)
wave with an amplitude of V_IN at the PHASE node. The
PWM wave is smoothed by the output filter (L_O and C_O).
The modulator transfer function is the small-signal transfer
function of V_OUT/V_E/A. This function is dominated by a DC
Gain and the output filter (L_O and C_O), with a double pole
break frequency at F_LC and a zero at F_ESR. The DC Gain of
the modulator is simply the input voltage (V_IN) divided by the
peak-to-peak oscillator voltage ∆V_OSC.