HI7188 Datasheet, PDF (7/22 Pages) Intersil Corporation – 8-Channel, 16-Bit, High Precision, Sigma-Delta A/D Sub-System

HI7188
Electrical Specifications
AV_DD = +5V, AV_SS = -5V, DV_DD = +5V, V_RHI = +2.5V, V_RLO = AGND, V_CM = AGND, PGIA Gain = 1,
OSC_IN = 3.6864MHz, Bipolar Input Range Selected (Continued)
-40^oC TO 85^oC
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNITS
Output Three-State Leakage
Current, I_OZ
Digital Output Capacitance, C_OUT
TIMING CHARACTERISTICS
V_OUT = 0V, +5V (Note 7)
(Note 2)
-
1
10
µA
-
10
-
pF
SCLK Minimum Cycle Time, t_SCLK
(Notes 2, 7)
SCLK Minimum Pulse Width, t_SCLKPW (Notes 2, 7)
CS to SCLK Precharge Time, t_PRE
(Notes 2, 7)
Data Setup to SCLK Rising Edge
(Write), t_DSU
(Notes 2, 7)
Data Hold from SCLK Rising Edge
(Write), t_DHLD
(Notes 2, 7)
Data Read Access from Instruction
Byte Write, t_ACC
(Notes 2, 7)
Read Bit Valid from SCLK Falling
Edge, t_DV
(Notes 2, 7)
Last Data Transfer to Data Ready
Inactive, t_DRDY
(Notes 2, 7)
RESET Low Pulse Width t_RESET
(Notes 2, 7)
RSTI/O Low Pulse Width t_RSTI/O
(Notes 2, 7)
MUX High Pulse Width t_MUX
(Notes 2, 7)
CADDR Valid to MUX High
(Notes 2, 7)
200
-
60
-
50
-
50
-
0
-
-
-
-
-
-
50
100
-
100
-
14
-
ns
-
ns
-
ns
-
ns
-
ns
40
ns
40
ns
-
ns
-
ns
-
ns
µs
75
ns
Oscillator Clock Frequency
(Notes 2, 7)
-
3.6864
-
MHz
Output Rise/Fall Time
(Notes 2, 7)
-
-
30
ns
Input Rise/Fall Time
(Notes 2, 7)
-
-
1
µs
POWER SUPPLY CHARACTERISTICS
IAV_DD
IAV_SS
IDV_DD
Power Dissipation, Active PD_A
AV_DD = +5V, OSC₁ = 3.6864MHz (Note 3)
-
AV_SS = -5V, OSC₁ = 3.6864MHz (Note 3)
-
DV_DD = +5V, SCLK = 4MHz
-
AV_DD = +5V, AV_SS = -5V, SLP = ‘0’
-
(Notes 3, 9)
1.8
3.0
mA
1.8
3.0
mA
2.0
4.0
mA
28
50
mW
Power Dissipation, Sleep PD_S
AV_DD = +5V, AV_SS = -5V, SLP = ‘1’
(Notes 3, 9)
-
5
-
mW
PSRR (∆ V_supply = 0.25V)
PSRR = 20log (∆V_supply / ∆V_OS ) (Note 3)
-
75
-
dB
NOTES:
2. Parameter guaranteed by design or characterization, not production tested.
3. DC PSRR is measured on all supplies individually and applies to both Bipolar and Unipolar Input Ranges.
4. These errors can be removed by re-calibrating at the desired operating temperature.
5. Applies after system calibration.
6. Fully differential input signal source is used.
7. See Load Test Circuit, Figure 1, R₁ = 10kΩ, C_L = 50pF (Includes Stray and Jig Capacitance).
8. For Line Noise Rejection, 3.6864MHz is required to develop internal clocks to reject 50/60Hz.
9. SLP is the sleep mode enable bit defined in bit 3 of the Control Register (CR <3>).
7-1853