HI7106_02 Datasheet, PDF (7/11 Pages) Intersil Corporation – 3 1/2 Digit, LCD/LED Display, A/D Converter

HI7106
a
a
a
a
fb
f bf b
gc
g
g
b
ec
ec ec
d
d
d
BACKPLANE
21
LCD PHASE DRIVER
TYPICAL SEGMENT OUTPUT
V+
0.5mA
2mA
SEGMENT
OUTPUT
INTERNAL DIGITAL GROUND
7
SEGMENT
DECODE
7
SEGMENT
DECODE
7
SEGMENT
DECODE
LATCH
1000’s
100’s
10’s
1’s
COUNTER COUNTER COUNTER COUNTER
TO SWITCH DRIVERS
FROM COMPARATOR OUTPUT
CLOCK
†
÷4
LOGIC CONTROL
† THREE INVERTERS
ONE INVERTER SHOWN FOR CLARITY
INTERNAL
DIGITAL
GROUND
V_TH = 1V
40
39
38
÷200
1
V+
6.2V
500Ω
TEST
37
26
V-
OSC 1
OSC 2
OSC 3
FIGURE 6. HI7106 DIGITAL SECTION
System Timing
Figure 7 shows the clocking arrangement used in the
HI7106. Two basic clocking arrangements can be used:
• Figure 7A. An external oscillator connected to pin 40.
• Figure 7B. An R-C oscillator using all three pins.
The oscillator frequency is divided by four before it clocks
the decade counters. It is then further divided to form the
three convert-cycle phases. These are signal integrate
(1000 counts), reference de-integrate (0 to 2000 counts) and
auto-zero (1000 to 3000 counts). For signals less than full
scale, auto-zero gets the unused portion of reference
de-integrate. This makes a complete measure cycle of 4,000
counts (16,000 clock pulses) independent of input voltage.
For three readings/second, an oscillator frequency of 48kHz
would be used.
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator
frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz,
40kHz, 33¹/₃kHz, etc. should be selected. For 50Hz
rejection, Oscillator frequencies of 200kHz, 100kHz,
66²/₃kHz, 50kHz, 40kHz, etc. would be suitable. Note that
7