HI3050 Datasheet, PDF (7/11 Pages) Intersil Corporation – Triple 10-Bit, 50 MSPS, High Speed, 3-Channel D/A Converter

HI3050
DAC INPUT/OUTPUT CODE TABLE (NOTE 1)
INPUT CODE
MSB
D9
D8
D7
D6
D5
D4
D3
D2
D1
1
1
1
1
1
1
1
1
1
•
•
•
1
0
0
0
0
0
0
0
0
•
•
•
0
0
0
0
0
0
0
0
0
NOTE:
1. V_REF = 2.0V, R_SET = 1.2K, R_LOAD = 75Ω.
LSB
D0
1
0
0
OUTPUT VOLTAGE
2.0V
1.0V
0V
Detailed Description
The HI3050 contains three matched, individual, 10 bit current
output digital-to-analog converters. The DACs can convert at
50MHz and run on +5V for both the analog and digital supplies.
The architecture is a current cell arrangement. 10-bit linearity is
obtained without laser trimming due to an internal calibration.
Digital Inputs
The digital inputs to the HI3050 have TTL level thresholds.
Due to the low input currents CMOS logic can be used as
well. The digital inputs are latched on the rising edge of the
clock.
To reduce switching noise from the digital data inputs, a
series termination resistor is the best solution. Using a 50Ω
to 130Ω resistor in series with the data lines, the edge rates
are slowed. Slower edge rates reduce the amount of over-
shoot and undershoot that directly couples through the lead
frame of the device. TTL drivers such as the 74ALS or 74F
series or CMOS logic series drivers, ACT, AC, or FCT, are
excellent for driving the TTL/CMOS inputs of the converter.
Clocks and Termination
The HI3050 clock rate can run to 50MHz, therefore, to minimize
reflections and clock noise into the part, proper termination
should be considered. In PCB layout clock traces should be kept
short and have a minimum of loads. To guarantee consistent
results from board to board controlled impedance traces should
be used with a characteristic line impedance.
To terminate the clock line, a shunt terminator to an AC ground
is the most effective type at a 50MHz clock rate. Shunt termi-
nation is best used at the receiving end of the transmission line
or as close to the HI3050 CLK pin as possible.
Z_O = 50Ω
CLK
R_T = 50Ω
HI3050
DAC
FIGURE 6. AC TERMINATION OF THE HI3050 CLOCK LINE
Rise and fall times and propagation delay of the line will be
affected by the Shunt Terminator. The terminator can be
connected to DGND.
Power Supplies
To reduce power supply noise, separate analog and digital
power supplies should be used with 0.1µF and 0.01µF ceramic
capacitors placed as close to the body of the HI3050 as
possible on the analog (AV_DD) and digital (DV_DD) supplies. The
analog and digital ground returns should be connected together
at the device to ensure proper operation on power up.
Reference
The HI3050 DACs have their own references and can be set
individually, see Figure 13. The three references can also
share a common reference voltage, see Figure 12. A shared
reference gives DAC to DAC matching of 1.5%, typically.
The HI3050 requires an external reference voltage to set the
full scale output current. The external reference voltage is
connected to the V_REF inputs (V_REFR, V_REFG, and
VREFB). The Full Scale Adjust input (FS ADJUST R, FS
ADJUST G, FS ADJUST B) should be connected to AGND
through a 1.2kΩ resistor, R_SET. The reference outputs
(V_REF OUT R, V_REF OUT G, V_REF OUT B) should be con-
nected to the decoupling input (COMP R, COMP G,
COMP B) and decoupled to AV_DD with a 0.1µF capacitor.
This improves settling time by decoupling switching noise
from the reference output of the HI3050.
The full scale output current is controlled by the voltage
reference pin and the set resistor (R_SET). The ratio is:
I_OUT (Full Scale) = (V_REF/R_SET) x 16, I_OUT is in mA
(EQ.1)
Blanking Input
The BLANK input, when pulled high, will force the outputs of
all three DACs to 0mA.
Chip Enable
The chip enable input, CE, will shut down the HI3050
causing the outputs to go to 0mA. The analog and digital
supply current will decrease to less than 1mA, reducing
power for low power applications.
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