DG441883 Datasheet, PDF (7/12 Pages) Intersil Corporation – Monolithic Quad SPST CMOS Analog Switches

DG441/883, DG442/883
Test Circuits
V_O is the steady state output with the switch on.
Feedthrough via switch capacitance may result in spikes at
the leading and trailing edge of the output waveform.
3V
LOGIC
INPUT
0V
SWITCH
INPUT
V_S
SWITCH
OUTPUT _0V
50%
t_R < 20ns (10% to 90% V_IN)
t_F < 20ns (90% to 10% V_IN)
t_OFF
V_O
0.8 V_O
0.8 V_O
t_ON
NOTE: Logic input waveform is inverted for switches that have
the opposite logic sense.
V+
SWITCH
INPUT
S₁
IN₁
D₁
V_O
LOGIC
INPUT
3V
GND
R_L
C_L
V-
Repeat test for Channels 2, 3 and 4.
For load conditions, see Specifications C_L (includes fixture and
stray capacitance)
VO
=
VS
---------------^R----^L----------------
RL + rDS_(ON)
FIGURE 1A.
FIGURE 1. SWITCHING TIME
FIGURE 1B.
Burn-In Circuit
DG441/883, DG442/883
V-
C₁
D₂ R₁
R₄
1 A₁
A_{2 16}
2 OUT₁ ^OUT2 15
3 IN₁
IN_{2 14}
4 V-
5 GND
6 IN₄
V+ ₁₃
V_REF
OPEN ¹²
IN_{3 11}
7 OUT₄ ^OUT3 10
8 A₄
A_{3 9}
V+
R₂
D₁ C₂
R₃
Spec Number 512044
65