CD4503BMS Datasheet, PDF (7/8 Pages) Intersil Corporation – CMOS Hex Buffer

CD4503BMS
Typical Performance Characteristics (Continued)
AMBIENT TEMPERATURE (T_A) = +25^oC
175
tPLH
150
tPHL
125
100
VDD = 5V
75
50
VDD = 10V
25
VDD = 15V
0 10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (CL) (pF)
AMBIENT TEMPERATURE (T_A) = +25^oC
70
60
50
40 _{5V (tTLH)}
30 ^{5V (tTHL)}
10V (tTLH)
20 _{15V (tTLH)}
10V (tTHL)
10
15V (tTHL)
0 10 20 30 40 50 60 70 80 90 100
LOAD CAPACITANCE (CL) (pF)
FIGURE 6. TYPICAL PROPAGATION DELAY TIME AS A
FUNCTION OF LOAD CAPACITANCE
FIGURE 7. TYPICAL TRANSITION TIME AS A FUNCTION OF
LOAD CAPACITANCE
8
6
4
2
10K ₈
6
4
2
1K
8
6
4
2
100
8
6
4
2
10
1
VDD = 5V
VDD = 10V
VDD = 15V
CL = 50pF
CL = 15pF
tr = tf = 20ns
AMBIENT TEMPERATURE (T_A) = +25^oC
2 4 68
2 4 68
2 4 68
2
10
10²
10³
FREQUENCY (f) (kHz)
4 68
10⁴
FIGURE 8. TYPICAL POWER DISSIPATION AS A FUNCTION OF FREQUENCY
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10^-3 inch).
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
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