ZL2105_14 Datasheet, PDF (6/36 Pages) Intersil Corporation – 3A Integrated Digital DC-DC Converter

2. Pin Descriptions
ZL2105
DGND 1
SYNC 2
SA ³
UVLO ⁴
ILIM ⁵
SCL ⁶
SDA ⁷
SALRT ⁸
XTEMP ⁹
ZL2105
Exposed Paddle
Connect to SGND
27 VR
26 BST
25 VDDP
24 VDDP
23 _SW
22 _SW
21 PGND
20 PGND
19 CP2
Figure 2. ZL2105 Pin Configurations (top view)
Table 4. Pin Descriptions
Pin
Label
Type¹ Description
1
DGND
PWR
Digital ground. Common return for digital signals. Connect to low impedance ground
plane.
Clock synchronization input. Used to set switching frequency of internal clock or for
2
SYNC I/O, M synchronization to external frequency reference. Programmable open drain output.
Factory default is push-pull
3
SA
I,M Serial address pin used to assign unique SMBus address to each IC.
4
UVLO
I,M Sets the input undervoltage lockout threshold that disables the device.
5
ILIM
I,M Sets the current limit threshold level.
6
SCL
I/O Serial clock signal for system communications.
7
SDA
I/O Serial data signal for system communications.
8
SALRT
O SMBus alert signal.
9
XTEMP
I
External temperature sensor input.
10,11
V0, V1
I,M Output voltage select pins. Used to set the output voltage.
12
DLY
I,M
Soft start delay select pin. Sets the delay from when EN is asserted until the output
voltage starts to ramp.
13
SS
I,M
Digital soft-start/stop. Sets the ramp period for the output to reach the desired regulation
point (after soft-start delay period, if applicable).
14
VTRK
I
Track input. Allows the output to track another voltage.
15
VSEN
I
Output voltage positive feedback sensing node.
16
NC
-
No internal connection.
17
VDR
PWR Supply pin for internal drivers.
18, 19 CP1,CP2
I/O Level-shift charge pump for 5 V operation. Connect external capacitor.
Notes:
1. I = Input, O = Output, PWR = Power or Ground. M = Multi-mode pins.
6
FN6851.2
March 30, 2011