ISL6620 Datasheet, PDF (6/10 Pages) Intersil Corporation – VR11.1 Compatible Synchronous Rectified Buck MOSFET Drivers

ISL6620, ISL6620A
Description
PWM
UGATE
t_PDHU
t_PDLU
t_RU
2.5V
1V
t_TSSHD
t_RU
t_FU
t_PTS
LGATE
1V
t_PTS
t_PDLL
t_RL
t_PDHL
t_TSSHD
t_FL
FIGURE 1. TIMING DIAGRAM
Operation and Adaptive Shoot-through Protection
Designed for high speed switching, the ISL6620, ISL6620A
MOSFET driver controls both high-side and low-side
N-Channel FETs from one externally provided PWM signal.
A rising transition on PWM initiates the turn-off of the lower
MOSFET (see Timing Diagram). After a short propagation
delay [t_PDLL], the lower gate begins to fall. Typical fall times
[t_FL] are provided in the “Electrical Specifications” table on
page 4. Adaptive shoot-through circuitry monitors the LGATE
voltage and turns on the upper gate following a short delay
time [t_PDHU] after the LGATE voltage drops below ~1V. The
upper gate drive then begins to rise [t_RU] and the upper
MOSFET turns on.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t_PDLU] is encountered before the upper gate
begins to fall [t_FU]. The adaptive shoot-through circuitry
monitors the UGATE-PHASE voltage and turns on the lower
MOSFET a short delay time [t_PDHL], after the upper MOSFET’s
gate voltage drops below 1V. The lower gate then rises [t_RL],
turning on the lower MOSFET. These methods prevent both the
lower and upper MOSFETs from conducting simultaneously
(shoot-through), while adapting the dead time to the gate
charge characteristics of the MOSFETs being used.
This driver is optimized for voltage regulators with large step
down ratio. The lower MOSFET is usually sized larger
compared to the upper MOSFET because the lower MOSFET
conducts for a longer time during a switching period. The
lower gate driver is therefore sized much larger to meet this
application requirement. The 0.4Ω ON-resistance and 4A sink
current capability enable the lower gate driver to absorb the
current injected into the lower gate through the drain-to-gate
capacitor of the lower MOSFET and help prevent
shoot-through caused by the self turn-on of the lower
MOSFET due to high dV/dt of the switching node.
Advanced PWM Protocol (Patent Pending)
The advanced PWM protocol of ISL6620, ISL6620A is
specifically designed to work with Intersil VR11.1 controllers.
When ISL6620, ISL6620A detects a PSI protocol sent by an
Intersil VR11.1 controller, it turns on diode emulation
operation; otherwise, it remains in normal CCM PWM mode.
The controller communicates the tri-state signal to the driver
by transitioning the PWM signal from 0V to 2V. The driver
recognizes Diode Emulation mode and after 330ns
(typically) evaluates the PHASE voltage to detect negative
current, thus turning off LGATE. With no further PWM pulses
from the controller, both UGATE and LGATE are low and the
output can shut down. This feature helps prevent a negative
transient on the output voltage when the output is shut down,
eliminating the Schottky diode that is used in some systems
for protecting the load from reversed output voltage events.
Otherwise, the PWM rising and falling thresholds outlined in
the “Electrical Specifications” on page 4 determine when the
lower and upper gates are enabled.
Note that the LGATE will not turn off until the diode emulation
minimum LGATE ON-time of 350ns is expired for a PWM low
to tri-level (2.5V) transition.
Diode Emulation
Diode emulation allows for higher converter efficiency under
light-load situations. With diode emulation active, the
ISL6620, ISL6620A detects the zero current crossing of the
output inductor and turns off LGATE. This prevents the low
side MOSFET from sinking current and ensures that
discontinuous conduction mode (DCM) is achieved. The
LGATE has a minimum ON-time of 350ns in DCM mode.
6
FN6494.0
April 25, 2008