ISL6608_14 Datasheet, PDF (6/11 Pages) Intersil Corporation – Synchronous Rectified MOSFET Driver with Pre-Biased Load Startup Capability

ISL6608
Description
Theory of Operation
Designed for speed, the ISL6608 dual MOSFET driver controls
both high-side and low-side N-Channel FETs from one
externally provided PWM signal.
A rising edge on PWM initiates the turn-off of the lower
MOSFET (see Figure 1, Timing Diagram). After a short
propagation delay [t_PDLL], the lower gate begins to fall.
Typical fall times [t_FL] are provided in the Electrical
Specifications section. Adaptive shoot-through circuitry
monitors the LGATE voltage. When LGATE has fallen below
1V, UGATE is allowed to turn ON. This prevents both the
lower and upper MOSFETs from conducting simultaneously,
or shoot-through.
A falling transition on PWM indicates the turn-off of the upper
MOSFET and the turn-on of the lower MOSFET. A short
propagation delay [t_PDLU] is encountered before the upper
gate begins to fall [t_FU]. The upper MOSFET gate-to-source
voltage is monitored, and the lower gate is allowed to rise
after the upper MOSFET gate-to-source voltage drops below
1V. The lower gate then rises [t_RL], turning on the lower
MOSFET.
This driver is optimized for converters with large step down
compared to the upper MOSFET because the lower
MOSFET conducts for a much longer time in a switching
period. The lower gate driver is therefore sized much larger
to meet this application requirement.
The 0.5Ω on-resistance and 4A sink current capability
enable the lower gate driver to absorb the current injected to
the lower gate through the drain-to-gate capacitor of the
lower MOSFET and prevent a shoot through caused by the
high dv/dt of the phase node.
PWM
UGATE
LGATE
t_PDLL
t_PDHU
t_PDLU
t_RU
2.5V
t_FU
1V
t_TSSHD
t_RU
t_PTS
1V
t_FL
t_RL
t_PDHL
t_TSSHD
t_FL
FIGURE 1. TIMING DIAGRAM
t_FU
t_PTS
6