ISL6520 Datasheet, PDF (6/11 Pages) Intersil Corporation – Single Synchronous Buck Pulse-Width Modulation (PWM) Controller

ISL6520
Please note that the capacitors C_IN and C_O may each
represent numerous physical capacitors. Locate the ISL6520
within 3 inches of the MOSFETs, Q₁ and Q₂ . The circuit traces
for the MOSFETs’ gate and source connections from the
ISL6520 must be sized to handle up to 1A peak current.
Figure 4 shows the circuit traces that require additional layout
consideration. Use single point and ground plane construction
for the circuits shown. Minimize any leakage current paths on
the COMP/OCSET pin and locate the resistor, R_OSCET close
to the COMP/OCSET pin because the internal current source is
only 20µA. Provide local V_CC decoupling between VCC and
GND pins. Locate the capacitor, C_BOOT as close as practical to
the BOOT and PHASE pins. All components used for feedback
compensation should be located as close to the IC a practical.
BOOT
D₁
+5V
C_BOOT
ISL6520
PHASE
VCC _+5V
COMP/OCSET
C_VCC
GND
+V_IN
Q₁ L_O
Q₂
C_O
V_OUT
FIGURE 4. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Feedback Compensation
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V_OUT) is regulated to the Reference voltage level. The
error amplifier (Error Amp) output (V_E/A) is compared with
the oscillator (OSC) triangular wave to provide a pulse-
width modulated (PWM) wave with an amplitude of V_IN at
the PHASE node. The PWM wave is smoothed by the output
filter (L_O and C_O).
Modulator Break Frequency Equations
FLC=
---------------------1---------------------
2π x LO x CO
FESR=
---------------------1----------------------
2π x ESR x CO
The compensation network consists of the error amplifier
(internal to the ISL6520) and the impedance networks Z_IN
and Z_FB. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f_0dB) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f_0dB and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R₁, R₂,
R₃, C₁, C₂, and C₃) in Figure 7. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R₂/R₁) for desired converter bandwidth.
2. Place 1^ST Zero Below Filter’s Double Pole (~75% F_LC).
3. Place 2^ND Zero at Filter’s Double Pole.
4. Place 1^ST Pole at the ESR Zero.
5. Place 2^ND Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
OSC
PWM
COMPARATOR
-
∆ V_OSC
+
DRIVER
DRIVER
V_IN
L_O
PHASE _CO
V_OUT
Z_FB
V_E/A
-
+
Z_IN
ERROR ^REFERENCE
AMP
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C₂
C₁
R₂
Z_FB
V_OUT
Z_IN
C₃ R₃
COMP
-
+
R₁
FB
ISL6520
REFERENCE
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The modulator transfer function is the small-signal transfer
function of V_OUT/V_E/A. This function is dominated by a DC
Gain and the output filter (L_O and C_O), with a double pole
break frequency at F_LC and a zero at F_ESR. The DC Gain of
the modulator is simply the input voltage (V_IN) divided by the
peak-to-peak oscillator voltage ∆V_OSC.
Compensation Break Frequency Equations
F_Z1 = -2---_π------x-----R--1--₂------x-----C----₁-
F_Z2 = _2----π------x-----₍--R-----₁----+-1----R-----₃---₎----x-----C-----₃-
F_P1
=
---------------------------1-----------------------------
2π
x
R₂
x



C-C----_{11-----+x-----CC----2-2-}
F_P2 = -2---_π------x-----R--1--₃------x-----C----₃-
Figure 6 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 6. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
6
FN9009.4
October 4, 2005