ISL6413 Datasheet, PDF (6/12 Pages) Intersil Corporation – Triple Output Regulator with Single Synchronous Buck and Dual LDO

ISL6413
Electrical Specifications
Recommended operating conditions unless
Capacitors = 33nF for LDO1 and LDO2. T_A
otherwise noted.
= 25^oC. (Note 2)
V_IN = V_IN_LDO
(Continued)
=
PV_CC
=
3.3V,
Compensation
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNITS
PGOOD Output Leakage Current
PWM OUTPUT OVER VOLTAGE
V_OUT = 3.3V
-
0.01
0.1
µA
Over Voltage Threshold
28
33
38
%
NOTE:
3. Specifications at -40^oC and +85^oC are guaranteed by design/characterization, not production tested.
4. This is the V_IN current consumed when the device is active but not switching. Does not include gate drive current.
5. The dropout voltage is defined as V_IN - V_OUT, when V_OUT is 50mV below the value of V_OUT for V_IN = V_OUT + 0.5V.
6. The RESET timeout period is linear with CT at the slope of 2.5ms/nF. Thus, at 10nF (0.01µF) the RESET time is 25ms; at 1000nF (0.1µF) the
RESET time would be 250ms.
7. Guaranteed by design, not production tested.
Typical Performance Curves
V_IN
1V/DIV
1V/DIV
0V
1V/DIV
V_OUT1
0V
0V
TIME (ms)
(2ms/DIV)
FIGURE 1. PWM SOFTSTART
TIME (µs)
(0.5µs/DIV)
FIGURE 2. PWM PHASE NODE SWITCHING
20mV/
DIV
TIME (µs)
(2µs/DIV)
FIGURE 3. PWM OUTPUT RIPPLE WAVEFORMS
1.82
1.815
1.81
1.805
1.8
0
0.05
0.1
0.15
0.2
0.25
0.3
LOAD CURRENT (A)
FIGURE 4. PWM LOAD REGULATION
6