ISL6262_14 Datasheet, PDF (6/27 Pages) Intersil Corporation – Two-Phase Core Regulator for IMVP-6 Mobile CPUs

ISL6262 Gate Driver Timing Diagram
PWM
UGATE
t_PDHU
t_RU
ISL6262
t_FU
1V
LGATE
1V
t_FL
Functional Pin Description
t_RL
t_PDHL
48 47 46 45 44 43 42 41 40 39 38 37
PGOOD 1
PSI# 2
PGD_IN 3
RBIAS 4
VR_TT# 5
NTC 6
SOFT 7
OCSET 8
VW 9
COMP 10
FB 11
FB2 12
GND PAD
(BOTTOM)
36 BOOT1
35 UGATE1
34 PHASE1
33 PGND1
32 LGATE1
31 PVCC
30 LGATE2
29 PGND2
28 PHASE2
27 UGATE2
26 BOOT2
25 NC
13 14 15 16 17 18 19 20 21 22 23 24
PGOOD - Power good open-drain output. Will be pulled up
externally by a 680Ω resistor to VCCP or 1.9kΩ to 3.3V.
PSI# - Low load current indicator input. When asserted low,
indicates a reduced load-current condition, and product goes
into single phase operation.
PGD_IN - Digital Input. When asserted high, indicates
VCCP and VCC_MCH voltages are within regulation.
6
RBIAS - 147K resistor to VSS sets internal current
reference.
VR_TT# - Thermal overload output indicator with open-drain
output. Over temperature pull-down resistance is 10Ω.
NTC - Thermistor input to VRTT# circuit and a 60µA current
source is connected internally to this pin.
FN9199.2
May 15, 2006