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ISL5629 Datasheet, PDF (6/12 Pages) Intersil Corporation – Dual 8-bit, +3.3V, 130/210MSPS, CommLink TM High Speed D/A Converter
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ISL5629
Electrical Specifications
PARAMETER
AVDD = DVDD = +3.3V, VREF = Internal 1.2V, IOUTFS = 20mA, TA = 25°C for All Typical Values (Continued)
TA = -40°C TO 85°C
TEST CONDITIONS
MIN TYP MAX UNITS
AC CHARACTERISTICS (Using Figure 6 with RDIFF = 50Ω and RLOAD = 50Ω, Full Scale Output = -2.5dBm)
Spurious Free Dynamic Range,
SFDR Within a Window
fCLK = 210MSPS, fOUT = 80.8MHz, 30MHz Span (Notes 4, 7)
fCLK = 210MSPS, fOUT = 40.4MHz, 30MHz Span (Notes 4, 7)
-
62
-
dBc
-
66
-
dBc
fCLK = 130MSPS, fOUT = 20.2MHz, 20MHz Span (Notes 4, 7)
-
66
-
dBc
Spurious Free Dynamic Range,
SFDR to Nyquist (fCLK/2)
fCLK = 210MSPS, fOUT = 80.8MHz (Notes 4, 7)
fCLK = 210MSPS, fOUT = 40.4MHz (Notes 4, 7, 9)
-
50
-
dBc
-
58
-
dBc
fCLK = 200MSPS, fOUT = 20.2MHz, T = 25°C (Notes 4, 7)
56
62
-
dBc
fCLK = 200MSPS, fOUT = 20.2MHz, T = -40°C to 85°C (Notes 4, 7) 54
-
-
dBc
fCLK = 130MSPS, fOUT = 50.5MHz (Notes 4, 7)
-
52
-
dBc
fCLK = 130MSPS, fOUT = 40.4MHz (Notes 4, 7)
-
55
-
dBc
fCLK = 130MSPS, fOUT = 20.2MHz (Notes 4, 7)
-
65
-
dBc
fCLK = 130MSPS, fOUT = 10.1MHz, T = -40°C to 85°C (Notes 4, 7) 63
67
-
dBc
fCLK = 130MSPS, fOUT = 5.05MHz (Notes 4, 7)
-
67
-
dBc
fCLK = 100MSPS, fOUT = 40.4MHz (Notes 4, 7)
-
56
-
dBc
fCLK = 80MSPS, fOUT = 30.3MHz (Notes 4, 7)
-
59
-
dBc
fCLK = 80MSPS, fOUT = 20.2MHz (Notes 4, 7)
-
66
-
dBc
fCLK = 80MSPS, fOUT = 10.1MHz (Notes 4, 7, 9)
-
66
-
dBc
fCLK = 80MSPS, fOUT = 5.05MHz (Notes 4, 7)
-
67
-
dBc
fCLK = 50MSPS, fOUT = 20.2MHz (Notes 4, 7)
-
60
-
dBc
fCLK = 50MSPS, fOUT = 10.1MHz (Notes 4, 7)
-
66
-
dBc
fCLK = 50MSPS, fOUT = 5.05MHz (Notes 4, 7)
-
66
-
dBc
Spurious Free Dynamic Range,
fCLK = 210MSPS, fOUT = 28.3MHz to 45.2MHz, 2.1MHz Spacing,
-
58
-
dBc
SFDR in a Window with Eight Tones 50MHz Span (Notes 4, 7, 9)
fCLK = 130MSPS, fOUT = 17.5MHz to 27.9MHz, 1.3MHz Spacing,
-
60
-
dBc
35MHz Span (Notes 4, 7)
fCLK = 80MSPS, fOUT = 10.8MHz to 17.2MHz, 811kHz Spacing,
-
60
-
dBc
15MHz Span (Notes 4, 7)
fCLK = 50MSPS, fOUT = 6.7MHz to 10.8MHz, 490kHz Spacing,
10MHz Span (Notes 4, 7)
-
60
-
dBc
VOLTAGE REFERENCE
Internal Reference Voltage, VFSADJ
Internal Reference Voltage Drift
Pin 20 Voltage with Internal Reference
1.2 1.23 1.3
V
-
±40
-
ppm/°C
Internal Reference Output Current
Sink/Source Capability
Reference is not intended to drive an external load
-
0
-
µA
Reference Input Impedance
-
1
-
MΩ
Reference Input Multiplying Bandwidth (Note 7)
-
1.0
-
MHz
DIGITAL INPUTS D7-D0, CLK
Input Logic High Voltage with
3.3V Supply, VIH
Input Logic Low Voltage with
3.3V Supply, VIL
Sleep Input Current, IIH
Input Logic Current, IIH, IL
(Note 3)
(Note 3)
2.3
3.3
-
V
-
0
1.0
V
-25
-
+25
µA
-20
-
+20
µA
6
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