ISL43L410_06 Datasheet, PDF (6/11 Pages) Intersil Corporation – Ultra Low ON-Resistance, Low Voltage, Single Supply, DPDT Analog Switch

ISL43L410
Test Circuits and Waveforms (Continued)
V+
C
SIGNAL
GENERATOR
NO or NC
ANALYZER
R_L
ADD 0V or V+
COM
GND INH
R_ON = V₁/100mA
V_NX
NO or NC
100mA
V₁
V+
C
ADD ^{0V or V+}
COM
GND INH
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 4. OFF ISOLATION TEST CIRCUIT
SIGNAL
GENERATOR
V+
C
NO or NC
COM
50Ω
ADD
0V or V+
ANALYZER
R_L
COM
NC or NO
GND INH
N.C.
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
FIGURE 6. CROSSTALK TEST CIRCUIT
Repeat test for all switches.
FIGURE 5. R_ON TEST CIRCUIT
IMPEDANCE
ANALYZER
NO or NC
V+
C
ADD 0V or V+
COM
GND INH
Repeat test for all switches.
FIGURE 7. CAPACITANCE TEST CIRCUIT
Detailed Description
The ISL43L410 is a bidirectional, double pole/double throw
(DPDT) analog switch that offers precise switching capability
from a single 1.65V to 3.6V supply with low on-resistance
(0.25Ω) and high speed operation (t_ON = 12ns, t_OFF = 5ns).
The device is especially well suited for portable battery
powered equipment due to its low operating supply voltage
(1.65V), low power consumption (2.7µW max), low leakage
currents (60nA max), and the tiny DFN and MSOP packages.
The ultra low on-resistance and Ron flatness provide very low
insertion loss and distortion to applications that require signal
reproduction.
Supply Sequencing And Overvoltage Protection
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 8). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND. If these
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (see Figure 8). The resistor
limits the input current below the threshold that produces
6
FN6090.2
July 28, 2006