ISL3685 Datasheet, PDF (6/19 Pages) Intersil Corporation – 2.4GHz RF/IF Converter and Synthesizer

ISL3685
Phase Lock Loop Electrical Specifications (See Notes 4 through 12) (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Reference Oscillator Sensitivity, CMOS Inputs, Single
Ended or Complementary
-
CMOS
-
Note 7
Reference Oscillator Duty Cycle
CMOS Inputs
40
-
60
%
Charge Pump Sink/Source Current/Tolerance
250µA Selection ±25%
0.18
0.25
0.32
mA
Charge Pump Sink/Source Current/Tolerance
500µA Selection ±25%
0.375
0.50
0.625
mA
Charge Pump Sink/Source Current/Tolerance
750µA Selection ±25%
0.56
0.75
0.94
mA
Charge Pump Sink/Source Current/Tolerance
1mA Selection ±25%
0.75
1.0
1.25
mA
Charge Pump Sink/Source Mismatch
-
-
15
%
Charge Pump Output Compliance
Charge Pump Supply Voltage
Charge Pump V_CC = V_CC2
0.5
2.7
-
V_CC2 -0.5
V
-
3.6
V
Serial Interface Clock Width
High Level t_CWH
20
-
-
ns
Low Level t_CWL
20
-
-
ns
Serial Interface Data/Clk Set-Up Time t_CS
20
-
-
ns
Serial Interface Data/Clk Hold Time t_CH
10
-
-
ns
Serial Interface Clk/LE Set-Up Time t_ES
20
-
-
ns
Serial Interface LE Pulse Width t_EW
20
-
-
ns
NOTES:
4. The Serial data is clocked on the Rising Edge of the serial clock, MSB first. The serial Interface is active when LE is LOW. The serial Data is
latched into defined registers on the rising edge of LE.
5. As long as power is applied, all register settings will remain stored, including the power down state. The system may then come in and out of
the power down state without requiring the registers to be rewritten.
6. CMOS Reference Oscillator input levels are given in the General Electrical Specification section.
POWER ENABLE TRUTH TABLE
PLL_PE
PE1
PE2
(SERIAL BUS)
STATUS
0
0
1
Power Down State, PLL in Save Mode, Active Serial Interface
1
1
1
Receive State
1
0
1
Transmit State
0
1
1
PLL Inactive, Inactive RX, TX, Active Serial Interface
X
X
0
PLL Disabled, Disabled PLL Registers, Active Serial Interface
NOTE:
7. PLL_PE is controlled via the serial interface, and can be used to disable the synthesizer. The actual synthesizer control is a logic AND function
of PLL_PE and the result of the logic OR function of PE1 and PE2. PE1 and PE2 directly control the power enable functionality of the LO buffers.
PLL Synthesizer Table
REGISTER
DEFINITION
SERIAL BITS LSB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 MSB
R Counter
0
0 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) R(8) R(9) R(10) R(11) R(12) R(13) R(14) X (Don’t Care)
A/B Counter 0
1 A(0) A(1) A(2) A(3) A(4) A(5) A(6) B(0) B(1) B(2) B(3) B(4) B(5) B(6) B(7) B(8) B(9) B(10)
Operational
1
0 M(0) 0 M(2) M(3) M(4) M(5) M(6) M(7) M(8) 0 0 0 0 M(13) M(14) M(15) X X
Mode
6