ISL3259E_14 Datasheet, PDF (6/16 Pages) Intersil Corporation – 15kV ESD Protected, 100Mbps, 5V, PROFIBUS, Full Fail-safe, Transceivers

ISL3259E
Electrical Specifications Test Conditions: V_CC = 4.75V to 5.25V; Unless Otherwise Specified. Typicals are at V_CC = 5V, T_A = +25°C,
(Note 5). (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP MIN
MAX
(°C) (Note 14) TYP (Note 14) UNITS
Receiver Disable from Output
Low
t_LZ
R_L = 1kΩ, C_L = 15pF, SW = V_CC (Figure 6)
Full
-
-
12
ns
Time to Shutdown
t_SHDN (Note 10)
Full
60
Receiver Enable from Shutdown t_ZH(SHDN) R_L = 1kΩ, C_L = 15pF, SW = GND (Figure 6), Full
-
to Output High
(Notes 10, 12)
-
600
ns
-
1000
ns
Receiver Enable from Shutdown t_ZL(SHDN) R_L = 1kΩ, C_L = 15pF, SW = V_CC (Figure 6), Full
-
to Output Low
(Notes 10, 12)
-
1000
ns
NOTES:
5. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless
otherwise specified.
6. Supply current specification is valid for loaded drivers when DE = 0V.
7. Applies to peak current. See “Typical Performance Curves” starting on page 11 for more information.
8. Because of the shutdown feature, keep RE = 0 to prevent the device from entering SHDN.
9. Because of the shutdown feature, the RE signal high time must be short enough (typically <100ns) to prevent the device from entering SHDN.
10. These IC’s are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 60ns, the parts are guaranteed not
to enter shutdown. If the inputs are in this state for at least 700ns, the parts are guaranteed to have entered shutdown. See “Low Power
Shutdown Mode” on page 11.
11. Keep RE = VCC, and set the DE signal low time >700ns to ensure that the device enters SHDN.
12. Set the RE signal high time >700ns to ensure that the device enters SHDN.
13. This is the part-to-part skew between any two units tested with identical test conditions (Temperature, V_CC, etc.).
14. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
Test Circuits and Waveforms
V_CC ^DE
DI
Z
D
Y
V_OD
R_L/2
R_L/2 VOC
V_CC ^DE
DI
Z
D
Y
V_OD
375Ω
R_L = 60Ω
V_CM
-7V TO +12V
375Ω
FIGURE 1A. V_OD AND V_OC
FIGURE 1B. V_OD WITH COMMON MODE LOAD
FIGURE 1. DC DRIVER TEST CIRCUITS
6
FN6587.1
February 18, 2008