ISL3159E_15 Datasheet, PDF (6/16 Pages) Intersil Corporation – ±15kV ESD Protected, +125°C, 40Mbps, 5V,PROFIBUS™, Full Fail-safe, RS-485/RS-422 Transceiver

ISL3159E
Electrical Specifications Test Conditions: V_CC = 4.5V to 5.5V; unless otherwise specified. Typicals are at V_CC = 5V, T_A = +25°C,
(Note 8) (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP MIN
MAX
(°C) (Note 18) TYP (Note 18) UNIT
Receiver Enable to Output High
t_ZH R_L = 1kΩ, C_L = 15pF, SW = GND
(Figure 8, Note 12)
Full
-
-
12
ns
Receiver Enable to Output Low
t_ZL
R_L = 1kΩ, C_L = 15pF, SW = V_CC
(Figure 8, Note 12)
Full
-
-
12
ns
Receiver Disable from Output High t_HZ R_L = 1kΩ, C_L = 15pF, SW = GND (Figure 8)
Receiver Disable from Output Low t_LZ R_L = 1kΩ, C_L = 15pF, SW = V_CC (Figure 8)
Time to Shutdown
t_SHDN (Note 13)
Receiver Enable from Shutdown to t_ZH(SHDN) R_L = 1kΩ, C_L = 15pF, SW = GND
Output High
(Figure 8, Notes 13, 15)
Full
-
Full
-
Full
60
Full
-
-
12
ns
-
12
ns
-
600
ns
-
1000
ns
Receiver Enable from Shutdown to t_ZL(SHDN) R_L = 1kΩ, C_L = 15pF, SW = V_CC
Output Low
(Figure 8, Notes 13, 15)
Full
-
-
1000
ns
NOTES:
8. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise
specified.
9. Supply current specification is valid for loaded drivers when DE = 0V.
10. Applies to peak current. See “Typical Performance Curves” on page 8 for more information.
11. Because of the shutdown feature, keep RE = 0 to prevent the device from entering SHDN.
12. Because of the shutdown feature, the RE signal high time must be short enough (typically <100ns) to prevent the device from entering SHDN.
13. These IC’s are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 60ns, the parts are guaranteed not to
enter shutdown. If the inputs are in this state for at least 700ns, the parts are guaranteed to have entered shutdown. See “Low Power Shutdown
Mode” on page 12.
14. Keep RE = VCC, and set the DE signal low time >700ns to ensure that the device enters SHDN.
15. Set the RE signal high time >700ns to ensure that the device enters SHDN.
16. This is the part-to-part skew between any two units tested with identical test conditions (temperature, V_CC, etc.).
17. V_CC = 5V ±5%
18. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
Test Circuits and Waveforms
V_CC ^DE
DI
Z
D
Y
V_OD
R_L/2
R_L/2 VOC
V_CC ^DE
DI
Z
D
Y
V_OD
375Ω
R_L = 60Ω
V_CM
-7V TO +12V
375Ω
FIGURE 3A. V_OD AND V_OC
FIGURE 3B. V_OD WITH COMMON-MODE LOAD
FIGURE 3. DC DRIVER TEST CIRCUITS
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6
FN6364.2
August 25, 2015