ISL29023 Datasheet, PDF (6/14 Pages) Intersil Corporation – Integrated Digital Ambient Light Sensor with Interrupt Function

ISL29023
Acknowledge
An acknowledge (ACK) is a software convention used to indicate
a successful data transfer. The transmitting device releases the
SDA bus after transmitting 8-bits. During the ninth clock cycle,
the receiver pulls the SDA line LOW to acknowledge the reception
of the eight bits of data (refer to Figure 12). The ISL29023
responds with an ACK after recognition of a START condition
followed by a valid Identification Byte, and once again, after
successful receipt of an Address Byte. The ISL29023 also
responds with an ACK after receiving a Data byte of a write
operation. The master must respond with an ACK after receiving
a Data byte of a read operation
Device Addressing
Following a START condition, the master must output a Device
Address byte. The 7 MSBs of the Device Address byte are known as
the device identifier. The device identifier bits of ISL29023 are
internally hard-wired as “1000100”. The LSB of the Device Address
byte is defined as read or write (R/W) bit. When this R/W bit is a
“1”, a read operation is selected and when “0”, a write operation is
selected (refer to Figure 10). The master generates a START
condition followed by Device Address byte 1000100x (x as R/W)
and the ISL29023 compares it with the internal device identifier.
Upon a correct comparison, the device outputs an acknowledge
(LOW) on the SDA line (refer to Figure 12).
Write Operation
BYTE WRITE
In a byte write operation, ISL29023 requires the Device Address
byte, Register Address byte, and the Data byte. The master starts
the communication with a START condition. Upon receipt of the
Device Address byte, Register Address byte, and the Data byte,
the ISL29023 responds with an acknowledge (ACK). Following
the ISL29023 data acknowledge response, the master
terminates the transfer by generating a STOP condition.
ISL29023 then begins an internal write cycle of the data to the
volatile memory. During the internal write cycle, the device inputs
are disabled and the SDA line is in a high impedance state, so the
device will not respond to any requests from the master (refer to
Figure 11).
SIGNAL FROM
MASTER DEVICE
SIGNAL AT SDA
SIGNALS FROM
SLAVE DEVICE
S
T
A
R
DEVICE ADDRESS
BYTE
T
10001000
ADDRESS BYTE
S
DATA BYTE
T
O
P
A
A
A
C
C
C
K
K
K
FIGURE 11. BYTE WRITE SEQUENCE
1
0
0
0
1
0
0
R/W
DEVICE
ADDRESS BYTE
A7
A6
A5
A4
A3
A2
A1
A0
REGISTER
ADDRESS BYTE
D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE
FIGURE 10. DEVICE ADDDRESS, REGISTER ADDRESS, & DATA BYTE
BURST WRITE
The ISL29023 has a burst write operation, which allows the
master to write multiple consecutive bytes from a specific
address location. It is initiated in the same manner as the byte
write operation, but instead of terminating the write cycle after
the first Data byte is transferred, the master can write to the
whole register array. After the receipt of each byte, the ISL29023
responds with an acknowledge, and the address is internally
incremented by one. The address pointer remains at the last
address byte written. When the counter reaches the end of the
register address list, it “rolls over” and goes back to the first
Register Address.
SCL FROM
MASTER
SDA FROM
TRANSMITTER
SDA FROM
RECEIVER
START
8^th
CLk
9^th CLk
HIGH IMPEDANCE
DATA
STABLE
DATA
CHANGE
DATA
STABLE
ACK
STOP
FIGURE 12. START, DATA STABLE, ACKNOWLEDGE, AND STOP CONDITION
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FN6691.1
July 17, 2012