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| ISL267452_14 Datasheet, PDF (6/16 Pages) Intersil Corporation – 12-Bit, 555kSPS SAR ADC | |||
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ISL267452
Electrical Specifications VDD = +3.0V to +3.6V, fSCLK = 10MHz, fS = 555kSPS, VREF = 2.0V; VDD = +4.75V to +5.25V, fSCLK = 10MHz,
fS = 555kSPS, VREF = 2.5V; VCM = VREF, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature
range, -40°C to +85°C. (Continued)
ISL267452
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 7)
MAX
TYP
(Note 7) UNITS
ILEAK Input DC Leakage Current
CVIN Input Capacitance
REFERENCE INPUT
Track/Hold mode
-1
1
µA
13/5
pF
VREF VREF Input Voltage Range
VDD = 3V (1% tolerance for specified
performance)
2.0
V
VDD = 5V (1% tolerance for specified
performance)
2.5
V
ILEAK DC Leakage Current
CVREF VREF Input Capacitance
LOGIC INPUTS
Track/Hold mode
-1
1
μA
21/18.5
pF
VIH
Input High Voltage
VIL
Input Low Voltage
ILEAK Input Leakage Current
CIN
Input Capacitance
LOGIC OUTPUTS
2.4
V
0.8
V
-1
1
µA
10
pF
VOH
VOL
IOZ
COUT
Output High Voltage
Output Low Voltage
Floating-State Output Current
Floating-State Output Capacitance
Output Coding
ISOURCE = 200µA
ISINK = 200µA
VDD - 0.3
V
0.4
V
-1
1
µA
10
pF
Twoâs Complement
CONVERSION RATE
tCONV Conversion Time
tACQ Acquisition Time
fmax Throughput Rate
POWER REQUIREMENTS
fSCLK = 10MHz
1.6
µs
200
ns
555 kSPS
VDD Positive Supply Voltage Range
2.7
3.6
V
4.75
5.25
V
IDD
Positive Supply Input Current
Static
1
µA
Dynamic
3V
1250 µA
5V
1700 µA
Power Dissipation
Static Mode
VDD = 3V
3
µW
VDD = 5V
5
µW
Dynamic
VDD = 3V, fsmpl = 555kSPS
VDD = 5V, fsmpl = 555kSPS
NOTES:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
8. The absolute voltage applied to each analog input must be between GND and VDD to guarantee datasheet performance.
3.75 mW
8.5 mW
6
FN8255.0
July 26, 2012
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