ISL24202 Datasheet, PDF (6/12 Pages) Intersil Corporation – Programmable VCOM Calibrator with EEPROM

ISL24202
Application Information
LCD panels have a V_COM (common voltage) that must be precisely
set to minimize flicker. Figure 3 shows a typical V_COM adjustment
circuit using a mechanical potentiometer, and the equivalent
circuit replacement using the ISL24202. Having a digital counter
interface enables automatic, digital flicker minimization during
production test and alignment. After programming, the counter
interface is not needed again - the ISL24202 automatically powers
up with the correct V_COM voltage programmed previously.
The ISL24202 uses a digitally controllable potentiometer (DCP),
with 256 steps of resolution (Figure 4) to change the current
drawn at the OUT pin, which then changes the voltage created by
the R₁ - R₂ resistor divider (Figure 5). The OUT voltage can then be
buffered by an external amplifier (A2) to generate a buffered output
voltage (V_COM) capable of driving the V_COM input of an LCD panel.
The amount of current sunk is controlled by the setting of the
DCP, which is recalled at power-up from the ISL24202’s internal
EEPROM. The EEPROM is typically programmed during panel
manufacture. As noted in the “Electrical Specifications” section
on page 4, the ISL24202 requires a minimum AV_DD voltage of
10.8V for EEPROM programming, but will work in normal
operation down to 4.5V after the EEPROM has been
programmed, with no additional EEPROM writing.
AVDD
RA
RB
R1 = RA
R2 = RB+RC
RC
RSET = RARB + RARC
20RB
VCOM
VDD
AVDD
AVDD
ISL24202
R1
OUT ^IOUT
A2
SET
R2
RSET
VCOM
FIGURE 3. MECHANICAL ADJUSTMENT REPLACEMENT
DCP (Digitally Controllable Potentiometer)
The DCP controls the voltage that ultimately controls the SET
current. Figure 4 shows the relationship between the register
value and the DCP’s tap position. Note that a register value of 0
selects the first step of the resistor string. The output voltage of
the DCP is given in Equation 1:
V_DCP
=
⎛
⎝
R_-----e_---g_----i_--s_---t_---e_-2--r_-5--V_--6-a_----l_--u_----e_----+-----1_{--⎠⎞}
⎛
⎝
A_----2-V_{---0D----D--⎠⎞}
(EQ. 1)
AV_DD
19R
AV_DD
20
R
REGISTER VALUE
255
254
253
V_DCP
252
251
2
1
0
FIGURE 4. SIMPLIFIED SCHEMATIC OF DCP
Output Current Sink
Figure 5 shows the schematic of the OUT current sink. The
combination of amplifier A1, transistor Q1, and resistor R_SET
forms a voltage-controlled current source, with the voltage
determined by the DCP setting.
AVDD
AVDD
VDCP
A1
Q1
VSAT
OUT
IOUT
R1
VOUT
R2
SET
VSET = VDCP = IOUT * RSET
IOUT
RSET
FIGURE 5. CURRENT SINK CIRCUIT
The external R_SET resistor sets the full-scale (maximum) sink current
that can be pulled from the OUT node. The relationship between
I_OUT and Register Value is shown in Equation 2.
I_OUT
=
V_{----D----C---P--}
R_SET
=
⎛
⎝
R_-----e_---g_----i_--s_---t_---e_-2--r_-5--V_--6-a_----l_--u_----e_----+-----1_{--⎠⎞}
⎛
⎝
A_----2-V_{---0D----D--⎠⎞}
⎛
⎝
-_R----_S¹---_E---_T-_⎠⎞
(EQ. 2)
The maximum value of I_OUT can be calculated by substituting the
maximum register value of 255 into Equation 2, resulting in
Equation 3:
I_OUT(MAX)
=
----^A----^V---^D----^D-----
20 R_{S E T}
(EQ. 3)
Equation 2 can also be used to calculate the unit sink current
step size per Register Code, resulting in Equation 4:
I_STEP
=
----------------^A----^V----^D----^D-----------------
( 256 ) ( 20 ) ( R _{S E T} )
(EQ. 4)
6
FN7587.0
March 15, 2011