ICL7129_00 Datasheet, PDF (6/10 Pages) Intersil Corporation – 4½ Digit LCD, Single-Chip A/D Converter

ICL7129
mately 12mA while DGND has no source capability.
-
+
N
24
V+
3.2V
LOGIC
“LOW
SECTION
BATTERY”
P
28
5V
COMMON
36
DGND
not desired in an application it can easily be overridden by
connecting the pin to V+ (HI) or DGND (LO). This connection
will not damage the device because the output impedance of
these pins is quite high. A simplified schematic of these
input/output pins is shown in Figure 6. Since there is approx-
imately 500kΩ in series with the output driver, the pin (when
used as an output) can only drive very light loads such as
4000 series, 74CXX type CMOS logic, or other high input
impedance devices. The output drive capability of these four
pins is limited to 3µA, nominally, and the input switching
threshold is typically DGND + 2V.
N
23
V-
FIGURE 3. BIASING STRUCTURE FOR COMMON AND DGND
V+
EXTERNAL
LOGIC
24
ICL7129
36
DGND
I_LOGIC
23
V-
FIGURE 4. DGND SINK CURRENT
V+
EXTERNAL
LOGIC
EXTERNAL
LOGIC
CURRENT
24
ICL7129
-
+
36
DGND
23
V-
FIGURE 5. BUFFERED DGND
The “LOW BATTERY” annunciator of the display is turned
on when the voltage between V+ and V- drops below 7.2V
typically. The exact point at which this occurs is determined
by the 6.3V zener diode and the threshold voltage of the
N-Channel transistor connected to the V- rail in Figure 3. As
the supply voltage decreases, the N-Channel transistor
connected to the V-rail eventually turns off and the “LOW
BATTERY” input to the logic section is pulled HIGH, turning
on the “LOW BATTERY” annunciator.
I/O Ports
Four pins of the ICL7129 can be used as either inputs or out-
puts. The specific pin numbers and functions are described
in the Pin Description table. If the output function of the pin is
DP4/OR PIN 20
DP3/UR PIN 21
LATCH/HOLD PIN 22
CONTINUITY PIN 27
≈ 500kΩ
ICL7129
FIGURE 6. “WEAK OUTPUT”
LATCH/HOLD, Overrange, and Underrange Timing
The LATCH/HOLD output (pin 22) will be pulled low during
the last 100 clock cycles of each full conversion cycle. Dur-
ing this time the final data from the ICL7129 counter is
latched and transferred to the display decoder and multi-
plexer. The conversion cycle and LATCH/HOLD timing are
directly related to the clock frequency. A full conversion
cycle takes 30,000 clock cycles which is equivalent to
60,000 oscillator cycles. OverRange (OR pin 20) and Under-
Range (UR pin 21) outputs are latched on the falling edge of
LATCH/HOLD and remain in that state until the end of the
next conversion cycle. In addition, digits 1 through 4 are
blanked during overrange. All three of these pins are “weak
outputs” and can be overridden with external drivers or pull-
up resistors to enable their input functions as described in
the Pin Description table.
Instant Continuity
A comparator with a built-in 200mV offset is connected
directly between INPUT HI and INPUT LO of the ICL7129
(Figure 7). The CONTINUITY output (pin 27) will be pulled
high whenever the voltage between the analog inputs is less
than 200mV. This will also turn on the “CONTINUITY”
annunciator on the display. The CONTINUITY output may
be used to enable an external alarm or buzzer, thereby giv-
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