HSP50016-EV Datasheet, PDF (6/18 Pages) Intersil Corporation – DDC Evaluation Platform

HSP50016-EV
that the software automatically updates the control words
from the EVAL.CFG file upon entering the interactive mode.
Leaving the interactive mode is accomplished by typing
“quit” or “exit.”
DDCCMD gives the user the ability to control the evaluation
board via DOS batch files or system calls from a
programming language. The DDC_CHK6.BAT file discussed
in the System Test Section is an example of how the
Command Line Program might be used in a DOS batch file.
Configuration Jumpers
The Configuration Jumpers consists of the jumper headers
JP1-3 and JP5-20 as shown in Figure 1 and Table 1. Refer to
the evaluation board schematic found in the Appendices.
Most of these are self-explanatory, but the following bear
further discussion.
JP16
JP17
JP18
FIGURE 2. JUMPER CONFIGURATION IF CLOCK IS
SUPPLIED THROUGH P1 INPUT HEADER
JP15
JP16
JP17
JP18
FIGURE 3. JUMPER CONFIGURATION IF CLOCK IS
SUPPLIED THROUGH P2 OUTPUT HEADER
The jumpers JP16 and JP17 are used to select whether the
HSP50016's clock source is provided through the P1
connector or the P2 connector. If jumpers are inserted as
shown in Figure 2, a clock signal supplied through the
CLK_IN pin of the P1 input header drives a buffer whose
output clocks the HSP50016. The jumper inserted on JP16
feeds the buffered clock signal to the CLK_OUT pin of the P2
connector. If jumpers are inserted as shown in Figure 3, the
CLK_OUT pin of the P2 connector drives the clock buffer
which in turn drives the clock input of the HSP50016. The
jumper inserted between JP16 pin 2 and JP17 pin 2 allows
the CLKIN pin to be driven by the buffer output. NOTE: The
jumper placement shown in Figure 2 is the standard
configuration.
It is possible to configure the DDC so that the I, Q, IQCLK
and IQSTB outputs are in a high impedance state. Except for
IQSTB, these pins are pulled up on the evaluation board so
that they will not float under these conditions. Since IQSTB
can be either active high or low, it must be capable of being
pulled either way. JP19 determines whether IQSTB is pulled
up or down when it is three-stated. This jumper should be
installed such that IQSTB is pulled to its inactive state.
Note: The position of JP20 comes into play only when
parallel output from P2 is desired.
The jumper should be placed between pins 1 and 2 when
the DDC is configured for I followed by Q mode; the jumper
should be from JP20-2 to JP20-3 when I and Q are output
separately. The HSP50016-EV is shipped from the factory
with the default jumper configuration shown in Figure 1 and
Table 1. For the supplied software to properly control
operation of the HSP50016, it is assumed that the jumpers
are as specified in the default configuration; of course, once
the user is familiar with the operation of the board, this
configuration may be modified as required. The system test
software, DDCCHK, must be run using the default
configuration.
JP
1
2
3
5
6-13
14
15
16
17
18
19
20
TABLE 1. DESCRIPTION OF JUMPER CONNECTIONS
DESCRIPTION
DDC CLK driven from external source when this jumper is installed.
DDC CLK driven from on board oscillator when this jumper is installed.
DDC CLK driven from PC software when this jumper is installed.
Only one of
JP1, JP2 and JP3
selected
at a time.
DDC DATA0-15 driven from PC software when installed, otherwise data is from external source. Must be
installed or DATA0-15 lines must be driven to avoid damage to DDC.
Selects evaluation board address. Only one of these jumpers should be installed at a time.
Selects input clock as inverted. Installed = non-inverted.
Selects output clock as inverted. Installed = non-inverted.
Direct flow of input and output clocks. JP16-1 is shorted to JP16-2 and JP17-1 is shorted to JP17-2 for the
DDC CLK to be driven by the PC, on board oscillator, or connector pin P1C-20. To drive CLK from P2C-
20, jumper JP16-1 to JP17-1 and JP16-2 to JP17-2. JP1 must be installed in this configuration.
TAP inputs driven by PC (installed) or from P2 (not installed).
IQSTB pulled up (JP19-1 shorted to JP19-2) or pulled down (JP19-2 to JP19-3). Must be installed (in ei-
ther position) to avoid damage to evaluation board.
Serial to parallel converters configured for up to 32-bit, I followed by Q (JP20-1 to JP20-2) or 16 bit, I and
Q output separately (JP20-2 to JP20-3).
DEFAULT
-
-
Installed
Installed
JP6 Installed
Installed
Installed
JP16-1 to JP16-2,
JP17-1 to JP17-2
Installed
JP19-1 to JP19-2
JP20-2 to JP20-3
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