HIP6004D_05 Datasheet, PDF (6/14 Pages) Intersil Corporation – Buck and Synchronous-Rectifier (PWM) Controller and Output Voltage Monitor

HIP6004D
GND (Pin 11)
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
PGOOD (Pin 12)
PGOOD is an open collector output used to indicate the
status of the converter output voltage. This pin is pulled low
when the converter output is not within ±10% of the
DACOUT reference voltage. Exception to this behavior is the
‘11111’ VID pin combination which disables the converter; in
this case PGOOD asserts a high level.
PHASE (Pin 13)
Connect the PHASE pin to the upper MOSFET source. This
pin is used to monitor the voltage drop across the MOSFET
for over-current protection. This pin also provides the return
path for the upper gate drive.
UGATE (Pin 14)
Connect UGATE to the upper MOSFET gate. This pin
provides the gate drive for the upper MOSFET.
BOOT (Pin 15)
This pin provides bias voltage to the upper MOSFET driver.
A bootstrap circuit may be used to create a BOOT voltage
suitable to drive a standard N-Channel MOSFET.
PGND (Pin 16)
This is the power ground connection. Tie the lower MOSFET
source to this pin.
LGATE (Pin 17)
Connect LGATE to the lower MOSFET gate. This pin
provides the gate drive for the lower MOSFET.
V_CC (Pin 18)
Provide a 12V bias supply for the chip to this pin.
OVP (Pin 19)
The OVP pin can be used to drive an external SCR in the
event of an overvoltage condition. Output rising 15% more
than the DAC-set voltage triggers a high output on this pin
and disables PWM gate drive circuitry.
RT (Pin 20)
This pin provides oscillator switching frequency adjustment.
By placing a resistor (R_T) from this pin to GND, the nominal
200kHz switching frequency is increased according to the
following equation:
Fs
≈
200 k H z
+
-⁵-----^x------¹---⁰---⁶--
R_T(kΩ)
(R_T to GND)
Conversely, connecting a pull-up resistor (R_T) from this pin
to V_CC reduces the switching frequency according to the
following equation:
Fs
≈
200 k H z
–
-⁴-----^x------¹---⁰---⁷--
R_T(kΩ)
(R_T to 12V)
Functional Description
Initialization
The HIP6004D automatically initializes upon receipt of power.
Special sequencing of the input supplies is not necessary. The
Power-On Reset (POR) function continually monitors the input
supply voltages. The POR monitors the bias voltage at the VCC
pin and the input voltage (V_IN) on the OCSET pin. The level on
OCSET is equal to V_IN less a fixed voltage drop (see over-
current protection). The POR function initiates soft start
operation after both input supply voltages exceed their POR
thresholds. For operation with a single +12V power source, V_IN
and V_CC are equivalent and the +12V power source must
exceed the rising VCC threshold before POR initiates
operation.
Soft Start
The POR function initiates the soft start sequence. An internal
10µA current source charges an external capacitor (C_SS) on
the SS pin to 4V. Soft start clamps the error amplifier output
(COMP pin) and reference input (+ terminal of error amp) to the
SS pin voltage. Figure 3 shows the soft start interval with
C_SS = 0.1μF. Initially the clamp on the error amplifier (COMP
pin) controls the converter’s output voltage. At t₁ in Figure 3,
the SS voltage reaches the valley of the oscillator’s triangle
wave. The oscillator’s triangular waveform is compared to the
ramping error amplifier voltage. This generates PHASE pulses
of increasing width that charge the output capacitor(s). This
interval of increasing pulse width continues to t₂. With sufficient
output voltage, the clamp on the reference input controls the
output voltage. This is the interval between t₂ and t₃ in Figure 3.
At t₃ the SS voltage exceeds the DACOUT voltage and the
output voltage is in regulation. This method provides a rapid
and controlled output voltage rise. The PGOOD signal toggles
‘high’ when the output voltage (VSEN pin) is within ±10% of
DACOUT. The 2% hysteresis built into the power good
comparators prevents PGOOD oscillation due to nominal
output voltage ripple.
PGOOD
(2V/DIV)
0V
SOFT-START
(1V/DIV)
OUTPUT
VOLTAGE
(1V/DIV)
0V
0V
t₁
t₂
t₃
TIME (5ms/DIV)
FIGURE 3. SOFT START INTERVAL
6
FN4855.3
July 13, 2005