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CDP1826C Datasheet, PDF (6/9 Pages) Intersil Corporation – CMOS 64-Word x 8-Bit Static RAM
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CDP1826C
Dynamic Electrical Specifications At TA = -40 to +85oC, VDD = 5V ±5%, Input tR, tF = 10ns; CL = 50pF and 1 TTL Load
LIMITS
CDP1826C
PARAMETER
(NOTE 1)
MIN
(NOTE 2)
TYP
MAX
UNITS
READ - CYCLE TIMES (FIGURES 4 AND 5)
Address to TPA Setup
tASH
100
-
-
ns
Address to TPA Hold
tAH
100
-
-
ns
Access from Address Change
TAA
-
500
1000
ns
TPA Pulse Width
tPAW
200
-
-
ns
Output Valid from MRD
tAM
-
500
1000
ns
Access from Chip Select
tAC
-
500
1000
ns
CEO Delay from TPA
Edge
tCA
-
150
300
ns
MRD to CEO Delay
tMC
75
-
-
ns
Output High Z from Invalid MRD
tRHZ
-
-
125
ns
Output High Z from Chip Deselect
tSHZ
-
-
225
ns
NOTES:
1. Time required by a limit device to allow tor the indicated function.
2. Typical values are or TA = 25oC and nominal VDD.
A0 - A5
TPA
MRD
CS1 - CS2
CEO
BUS
HIGH ORDER
ADDRESS BYTE
tASH
tAH
LOW ORDER ADDRESS BYTE
tAA
tPAW
tAC
VALID CHIP SELECT
tCA
tMC
HIGH IMPEDANCE
tAM
VALID DATA
FIGURE 4. TIMING WAVEFORMS FOR READ CYCLE 1
tRHZ
tSHZ
6-52
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