X95820 Datasheet, PDF (5/12 Pages) Intersil Corporation – Dual Digital Controlled Potentiometers

X95820
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (Note 1)
t_SU:DAT Input data setup time
t_HD:DAT Input data hold time
t_SU:STO STOP condition setup time
t_HD:STO STOP condition setup time
t_DH (Note 15) Output data hold time
t_R (Note 15) SDA and SCL rise time
From SDA exiting the 30% to 70% of V_CC
window, to SCL rising edge crossing 30% of V_CC
From SCL rising edge crossing 70% of V_CC to SDA
entering the 30% to 70% of V_CC window.
From SCL rising edge crossing 70% of V_CC, to SDA
rising edge crossing 30% of V_CC.
From SDA rising edge to SCL falling edge. Both
crossing 70% of V_CC.
From SCL falling edge crossing 30% of V_CC, until
SDA enters the 30% to 70% of V_CC window.
From 30% to 70% of V_CC
100
0
600
600
0
20 +
0.1 * Cb
t_F (Note 15) SDA and SCL fall time
From 70% to 30% of V_CC
20 +
0.1 * Cb
Cb (Note 15) Capacitive loading of SDA or Total on-chip and off-chip
10
SCL
Rpu (Note 15) SDA and SCL bus pull-up Maximum is determined by t_R and t_F.
1
resistor off-chip
For Cb = 400pF, max is about 2~2.5kΩ.
For Cb = 40pF, max is about 15~20kΩ.
t_WP
Non-volatile Write cycle time
12
(Notes 15, 16)
t_SU:WPA A2, A1, A0, and WP setup Before START condition
600
time
t_HD:WPA A2, A1, A0, and WP hold After STOP condition
600
time
MAX
250
250
400
20
SDA vs. SCL Timing
t_F
t_HIGH
t_LOW
t_R
UNITS
ns
ns
ns
ns
ns
ns
ns
pF
kΩ
ms
ns
ns
SCL
t_SU:STA
SDA
(Input Timing)
SDA
(Output Timing)
t_SU:DAT
t_HD:STA
t_HD:DAT
t_AA t_DH
t_SU:STO
t_BUF
WP, A0, A1, and A2 Pin Timing
START
SCL
Clk 1
STOP
SDA IN
WP, A0, A1, or A2
t_SU:WPA
t_HD:WPA
5
FN8212.1
September 26, 2005