X9271 Datasheet, PDF (5/22 Pages) Xicor Inc. – Single Digitally-Controlled (XDCP) Potentiometer

X9271
PRINCIPLES OF OPERATION
Device Description
SERIAL INTERFACE
The X9271 supports the SPI interface hardware
conventions. The device is accessed via the SI input
with data clocked in on the rising SCK. CS must be
LOW and the HOLD and WP pins must be HIGH
during the entire operation.
The SO and SI pins can be connected together, since
they have three state outputs. This can help to reduce
system pin count.
ARRAY DESCRIPTION
The X9271 is comprised of a resistor array (See
Figure 1). The array contains the equivalent of 255
discrete resistive segments that are connected in
Figure 1. Detailed Potentiometer Block Diagram
series. The physical ends of each array are equivalent
to the fixed terminals of a mechanical potentiometer
(R_H and R_L inputs).
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper
(R_W) output. Within each individual array only one
switch may be turned on at a time.
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select, and enable, one of 256
switches (See Table 1).
POWER-UP AND DOWN RECOMMENDATIONS.
There are no restrictions on the power-up or power-
down conditions of V_CC and the voltages applied to
the potentiometer pins provided that V_CC is always
more positive than or equal to V_H, V_L, and V_W, i.e.,
V_CC ≥ V_H, V_L, V_W. The V_CC ramp rate specification is
always in effect.
SERIAL DATA PATH
SERIAL
R_H
FROM INTERFACE
CIRCUITRY
BUS
INPUT
REGISTER 0
REGISTER 1
C
(DR0)
(DR1)
O
U
8
BANK_0 Only
8
PARALLEL
BUS
INPUT
N
T
E
R
REGISTER 2
(DR2)
REGISTER 3
(DR3)
WIPER
D
COUNTER
E
C
REGISTER
(WCR)
O
D
E
IF WCR = 00[H] THEN R_W = R_L
IF WCR = FF[H] THEN R_W = R_H
UP/DN
INC/DEC
LOGIC
UP/DN
MODIFIED SCK _CLK
R_L
R_W
5
FN8174.1
March 31, 2005