X9111 Datasheet, PDF (5/18 Pages) Xicor Inc. – Single Digitally-Controlled Potentiometer

X9111
A1–A0 input pins. The slave address is externally specified
by the user. The X9111 compares the serial data stream with
the address input state; a successful compare of the address
bits is required for the X9111 to successfully continue the
command sequence. Only the device whose slave address
matches the incoming device address sent by the master
executes the instruction. The A1–A0 inputs can be actively
driven by CMOS input signals or tied to V_CC or V_SS. The
R/W bit is used to set the device to either read or write
mode.
Instruction Byte and Register Selection
The next byte sent to the X9111 contains the instruction and
register pointer information. The three most significant bits
are used provide the instruction opcode (I[2:0]). The RB and
RA bits point to one of the four registers. The format is
shown in Table 5.
TABLE 1. WIPER LATCH, WL (10-BIT), WCR9–WCR0: USED TO STORE THE CURRENT WIPER POSITION (VOLATILE, V)
WCR9
WCR8
WCR7
WCR6
WCR5
WCR4
WCR3
WCR2
WCR1
WCR0
V
V
V
V
V
V
V
V
V
V
(MSB)
(LSB)
TABLE 2. DATA REGISTER, DR (10-BIT), BIT 9–BIT 0: USED TO STORE WIPER POSITIONS OR DATA (NON-VOLATILE, NV)
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
MSB
LSB
TABLE 3. STATUS REGISTER, SR (1-BIT)
WIP
(LSB)
ID3
0
(MSB)
TABLE 3. IDENTIFICATION BYTE FORMAT
Device Type
Identifier
Internal Slave
Address
ID2
ID1
ID0
0
A1
A0
1
0
1
Read or
Write Bit
R/W
(LSB)
I2
(MSB)
Instruction
Opcode
I1
TABLE 4. INSTRUCTION BYTE FORMAT
Register
Selection
I0
0
RB
RA
0
RB
RA REGISTER
0
0
0
1
1
0
1
1
DR0
DR1
DR2
DR3
0
(LSB)
5
FN8159.1
March 25, 2005