ISL6610_14 Datasheet, PDF (5/11 Pages) Intersil Corporation – Dual Synchronous Rectified MOSFET Drivers

ISL6610, ISL6610A
Electrical Specifications These specifications apply for T_A = -40°C to +85°C, unless otherwise noted (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP
UGATE Turn-On Propagation Delay
LGATE Turn-On Propagation Delay
Tri-state to UG/LG Rising Propagation Delay
OUTPUT (Note 4)
t_PDHU
t_PDHL
t_PTS
Outputs Unloaded
Outputs Unloaded
Outputs Unloaded
-
18
-
23
-
20
Upper Drive Source Resistance
R_{UG_SRC} 250mA Source Current
Upper Drive Sink Resistance
R_{UG_SNK} 250mA Sink Current
Lower Drive Source Resistance
R_{LG_SRC} 250mA Source Current
Lower Drive Sink Resistance
R_{LG_SNK} 250mA Sink Current
NOTE:
4. Guaranteed by Characterization. Not 100% tested in production.
-
1.0
-
1.0
-
1.0
-
0.4
MAX
-
-
-
2.5
2.5
2.5
1.0
UNITS
ns
ns
ns
Ω
Ω
Ω
Ω
Functional Pin Description
PACKAGE PIN #
PIN
SOIC DFN SYMBOL
FUNCTION
1
15
PWM1 The PWM signal is the control input for the Channel 1 driver. The PWM signal can enter three distinct states during
operation, see the Tri-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM
output of the controller.
2
16
PWM2 The PWM signal is the control input for the Channel 2 driver. The PWM signal can enter three distinct states during
operation, see the Tri-state PWM Input section under DESCRIPTION for further details. Connect this pin to the PWM
output of the controller.
3
1
GND Bias and reference ground. All signals are referenced to this node.
4
2
LGATE1 Lower gate drive output of Channel 1. Connect to gate of the low-side power N-Channel MOSFET.
5
3
PVCC This pin supplies power to both the lower and higher gate drives. Place a high quality low ESR ceramic capacitor
from this pin to PGND.
6
4
PGND Power ground return of both low gate drivers.
-
5,8
NC1,2 No connection.
7
6
LGATE2 Lower gate drive output of Channel 2. Connect to gate of the low-side power N-Channel MOSFET.
8
7
PHASE2 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 2. This
pin provides a return path for the upper gate drive.
9
9
UGATE2 Upper gate drive output of Channel 2. Connect to gate of high-side power N-Channel MOSFET.
10
10
BOOT2 Floating bootstrap supply pin for the upper gate drive of Channel 2. Connect the bootstrap capacitor between this
pin and the PHASE2 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the
Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value.
11
11
BOOT1 Floating bootstrap supply pin for the upper gate drive of Channel 1. Connect the bootstrap capacitor between this
pin and the PHASE1 pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the
Internal Bootstrap Device section under DESCRIPTION for guidance in choosing the capacitor value.
12
12 UGATE1 Upper gate drive output of Channel 1. Connect to gate of high-side power N-Channel MOSFET.
13
13 PHASE1 Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET in Channel 1. This
pin provides a return path for the upper gate drive.
14
14
VCC Connect this pin to a +5V bias supply. It supplies power to internal analog circuits. Place a high quality low ESR
ceramic capacitor from this pin to GND.
-
17
PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection.
5
FN6395.0
November 22, 2006