ISL6594D Datasheet, PDF (5/11 Pages) Intersil Corporation – Advanced Synchronous Rectified Buck MOSFET Drivers with Protection Features

ISL6594D
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNITS
UGATE Fall Time (Note 4)
LGATE Fall Time (Note 4)
UGATE Turn-On Propagation Delay (Note 4)
LGATE Turn-On Propagation Delay (Note 4)
UGATE Turn-Off Propagation Delay (Note 4)
LGATE Turn-Off Propagation Delay (Note 4)
LG/UG Three-State Propagation Delay (Note 4)
OUTPUT (Note 4)
t_FU
t_FL
t_PDHU
t_PDHL
t_PDLU
t_PDLL
t_PDTS
V_PVCC = 12V, 3nF Load, 90% to 10%
V_PVCC = 12V, 3nF Load, 90% to 10%
V_PVCC = 12V, 3nF Load, Adaptive
V_PVCC = 12V, 3nF Load, Adaptive
V_PVCC = 12V, 3nF Load
V_PVCC = 12V, 3nF Load
V_PVCC = 12V, 3nF Load
-
18
-
ns
-
12
-
ns
-
10
-
ns
-
10
-
ns
-
10
-
ns
-
10
-
ns
-
10
-
ns
Upper Drive Source Current
I_{U_SOURCE} V_PVCC = 12V, 3nF Load
Upper Drive Source Impedance
R_{U_SOURCE} 150mA Source Current
Upper Drive Sink Current
I_{U_SINK} V_PVCC = 12V, 3nF Load
Upper Drive Sink Impedance
R_{U_SINK} 150mA Sink Current
Lower Drive Source Current
I_{L_SOURCE} V_PVCC = 12V, 3nF Load
Lower Drive Source Impedance
R_{L_SOURCE} 150mA Source Current
Lower Drive Sink Current
I_{L_SINK} V_PVCC = 12V, 3nF Load
Lower Drive Sink Impedance
R_{L_SINK} 150mA Sink Current
NOTE:
4. Guaranteed by Characterization. Not 100% tested in production.
-
1.25
-
A
1.4
2.0
3.0
Ω
-
2
-
A
0.9 1.65 3.0
Ω
-
2
-
A
0.85
1.3
2.2
Ω
-
3
-
A
0.60 0.94 1.35
Ω
Functional Pin Description
PACKAGE PIN #
PIN
SOIC DFN SYMBOL
FUNCTION
1
1
UGATE Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
2
2
BOOT Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the Internal Bootstrap
Device section under Description for guidance in choosing the capacitor value.
-
3, 8
N/C No Connection.
3
4
PWM The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see
the three-state PWM Input section under Description for further details. Connect this pin to the PWM output of the
controller.
4
5
GND Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
5
6
LGATE Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
6
7
VCC Its operating range is +6.8V to 13.2V. Place a high quality low ESR ceramic capacitor from this pin to GND.
7
9
PVCC This pin supplies power to both upper and lower gate drives. Its operating range is +4.5V to 13.2V. Place a high
quality low ESR ceramic capacitor from this pin to GND.
8
10
PHASE Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
9
11
PAD Connect this pad to the power ground plane (GND) via thermally enhanced connection.
5
FN9282.0
March 30, 2006