ISL6528 Datasheet, PDF (5/13 Pages) Intersil Corporation – Dual Regulator - Standard Buck PWM and Linear Power Controller

ISL6528
Functional Pin Descriptions
GND 1
VCC 2
DRIVE2 3
FB2 4
8 UGATE
7 BOOT
6 COMP
5 FB
GND (Pin 1)
Signal ground for the IC. All voltage levels are measured
with respect to this pin. Place via close to pin to minimize
impedance path to ground plane.
VCC (Pin 2)
Provide a well decoupled 5V bias supply for the IC to this
pin. The voltage at this pin is monitored for Power-On Reset
(POR) purposes.
DRIVE2 (Pin 3)
Connect this pin to the base terminal of an external bipolar
NPN transistor. This pin provides the base current drive for
the linear regulator pass transistor.
FB2 (Pin 4)
Connect the output of the linear regulator to this pin through
a properly sized resistor divider. The voltage at this pin is
regulated to 0.8V. This pin is also monitored for undervoltage
events.
Pulling and holding FB2 above 1.25V shuts down both
regulators. Releasing FB2 initiates soft-start on both
regulators.
FB (Pin 5) and COMP (Pin 6)
FB and COMP are the available external pins of the error
amplifier. The FB pin is the inverting input of the error amplifier
and the COMP pin is the error amplifier output. These pins are
used to compensate the voltage-mode control feedback loop of
the standard buck converter.
BOOT (Pin 7)
Connect a suitable capacitor (0.47µF recommended) from
this pin to the source terminal of the upper MOSFET
(PHASE node). This bootstrap capacitor supplies the
UGATE driver the energy necessary to turn and hold the
upper MOSFET on. The absolute maximum voltage on
BOOT must be kept below 10V. This can be met with a 5V
VCC and 3.3V drain supply to the upper MOSFET.
UGATE (Pin 8)
Connect UGATE to the upper MOSFET gate. This pin
provides the gate drive for the MOSFET.
Description
Operation Overview
The ISL6528 monitors and precisely controls two output
voltage levels. Refer to the Block Diagram, Simplified
Power System Diagram, and Typical Application Schematic
on pp. 2–3. The controller is intended for use in graphics
card or embedded processor applications with 3.3V and 5V
bias input available. The IC integrates both a standard buck
PWM controller and a linear controller. The PWM controller
is designed to regulate the high current GPU voltage
(V_OUT1). The PWM controller drives a single N-Channel
MOSFET (Q1) in a standard buck converter configuration
and regulates the output voltage to a level programmed by
a resistor divider. The linear controller is designed to
regulate the lower current local memory voltage (V_OUT2)
through an external NPN pass transistor.
Initialization
The ISL6528 automatically initializes upon application of
input power. Special sequencing of the input supplies is not
necessary. The POR function continually monitors the input
bias supply voltage at the VCC pin. The POR function
initiates soft-start operation after the 5V bias supply voltage
exceeds its POR threshold.
Soft-Start
The POR function initiates the digital soft-start sequence.
Both the linear regulator error amplifier and PWM error
amplifier reference inputs are forced to track a voltage level
proportional to the soft-start voltage. As the soft-start voltage
slews up, the PWM comparator regulates the output relative
to the tracked soft-start voltage slowly charging the output
capacitor(s). Simultaneously, the linear output follows the
smooth ramp of the soft-start function into normal regulation.
Figure 1 shows the soft-start sequence for a typical application.
At T0, the +5V VCC bias voltage starts to ramp followed by the
3.3V input supply. Once the voltage on VCC crosses the 4.4V
POR threshold at time T1, both outputs begin their soft-start
sequence. The triangle waveform from the PWM oscillator is
compared to the rising error amplifier output voltage. As the
error amplifier voltage increases, the pulse-width on the
UGATE pin increases to reach its steady-state duty cycle at
time T2. The error amplifier reference of the linear controller
also rises relative to the soft-start reference. The resulting soft
ramp on DRIVE2 brings V_OUT2 within regulation limits by time
T2.
Undervoltage Protection
The FB and FB2 pins are monitored during converter
operation by two separate undervoltage (UV) comparators. If
the FB voltage drops below 52.5% of the reference voltage
(0.42V), a fault signal is generated. The internal fault logic
5
FN9038.3
December 28, 2004