ISL6506 Datasheet, PDF (5/8 Pages) Intersil Corporation – Multiple Linear Power Controller with ACPI Control Interface

ISL6506, ISL6506A, ISL6506B
5VSB
S3
S5
3.3V, 5V, 12V
DLA
3V3DL
5VDLSB
5VDL
FIGURE 2. 5V_DUAL AND 3.3V_AUX TIMING DIAGRAM;
ISL6506A
Soft-Start
Figures 3 and 4 show the soft-start sequence for the typical
application start-up into a sleep state. At time t0, 5V_SB (bias)
is applied to the circuit. At time t1, the 5V_SB surpasses POR
level. Time t2, one soft-start interval after t1, denotes the
initiation of soft-start. The 3.3V_DUAL rail is brought up
through the internal standby LDO through an internal digital
soft-start function. Figure 4 shows the 5V_DUAL rail initiating a
soft-start at time t2 as well. The ISL6506A will draw 7.5µA
into the 5VDLSB for a duration of one soft-start period. This
current will enhance the P-MOSFET (Q₂, refer to “Typical
Application” on page 2) in a controlled manner. At time t3,
the 3.3V_DUAL is in regulation and the 5VDLSB pin is pulled
down to ground. If the 5V_DUAL rail has not reached the level
of the 5V_SB rail by time t3, then the rail will experience a
sudden step as the P-MOSFET gate is fully enhanced. The
soft-start profile of the 5V_DUAL may be altered by placing a
capacitor between the gate and drain of the P-MOSFET.
Adding this capacitor will increase the gate capacitance and
slow down the start of the 5V_DUAL rail.
At time t4, the system has transitioned into S0 state and the
ATX supplies have begun to ramp-up. With the ISL6506,
ISL6506B (Figure 3), the 5V_DUAL rail will begin to ramp-up
from the 5V_ATX rail through the body diode of the N-MOSFET
(Q₃). The ISL6506A will already have the 5V_DUAL rail in
regulation (Figure 4). At time t5, the 12V_ATX rail has
surpassed the 12V POR level. Time t6 is three soft-start
cycles after the 12V POR level has been surpassed. At time
t6, three events occur simultaneously. The DLA pin is forced
to a high impedance state which allows the 12V rail to
enhance the two N-MOSFETs (Q₁ and Q₃) that connect the
ATX rails to the 3.3V_DUAL and 5V_DUAL rails. The 5VDLSB pin
is actively pulled high, which will turn the P-MOSFET (Q₂) off.
Finally, the internal LDO which regulates the 3.3V_AUX rail in
sleep states is put in standby mode.
5
5VSB
(1V/DIV)
12VATX (2V/DIV)
5VATX (1V/DIV)
3.3VATX (1V/DIV)
3.3VDUAL
(2V/DIV)
5VDUAL
(1V/DIV)
0V
DLA
(10V/DIV)
t0 t1 t2 t3
t4 t5
t6
TIME
FIGURE 3. ISL6506 AND ISL6506B SOFT-START INTERVAL
IN S4/S5 STATE AND S5 TO S0 TRANSITION
5VSB
(1V/DIV)
5VDUAL
(1V/DIV)
3.3VDUAL
(2V/DIV)
12VATX (2V/DIV)
5VATX (1V/DIV)
3.3VATX (1V/DIV)
0V
5VDLSB
(5V/DIV)
DLA
(10V/DIV)
t0 t1 t2 t3
t4 t5
t6
TIME
FIGURE 4. SOFT-START INTERVAL FOR ISL6506A IN S4/S5
AND S5 TO S0 TRANSITION FOR ISL6506A AND
S3 TO S0 TRANSITION FOR ISL6506, ISL6506A,
ISL650B
Sleep to Wake State Transitions
Figures 3 and 4, starting at time t4, depict the transitions
from sleep states to the S0 wake state. Figure 3 shows the
transition of the ISL6506, ISL6506B from the S4/S5 state to
the S0 state. Figure 4 shows how the ISL6506, ISL6506B
will transition from the S3 sleep state into S0 state. Figure 3
also shows how the ISL6506A transitions from either S3 or
S4/S5 in the S0 state. For all transitions, t4 depicts the
system transition into the S0 state. Here, the ATX supplies
are enabled and begin to ramp up. At time t5, the 12V_ATX rail
has exceeded the POR threshold for the ISL6506, ISL6506B
and ISL6506A. Three soft-start periods after time t5, at time
t6, three events occur simultaneously. The DLA pin is forced
FN9141.3
May 7, 2008