ISL6414 Datasheet, PDF (5/12 Pages) Intersil Corporation – Triple Output, Low-Noise LDO Regulator with Integrated Reset Circuit

ISL6414
Electrical Specifications V_IN = +3.3V, Compensation Capacitor = 33nF, T_A = 25°C, Unless Otherwise Noted. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Output Voltage Noise
LDO3 SPECIFICATIONS
10Hz < f < 100kHz, I_OUT = 10mA
C_OUT = 2.2µF
-
65
-
µV_RMS
C_OUT = 10µF
-
60
-
µV_RMS
Output Voltage (V_OUT3)
Output Voltage Accuracy
Maximum Output Current (I_OUT3) (Note 6)
Output Current Limit (Note 6)
I_OUT = 10mA
V_IN = 3.6V
-
2.84
-
V
-1.5
-
1.5
%
200
-
-
mA
250
400
-
mA
Dropout Voltage (Note 4)
Line Regulation
Load Regulation
Output Voltage Noise
RESET BLOCK SPECIFICATIONS
I_OUT = 200mA
-
100
200
mV
V_IN = 3.0V to 3.6V, I_OUT = 10mA
-0.15
0.0
0.15
%/V
I_OUT = 10mA to 200mA
-
0.2
1.0
%
10Hz < f < 100kHz, I_OUT = 10mA
C_OUT = 2.2µF
-
30
-
µV_RMS
C_OUT = 10µF
-
20
-
µV_RMS
RESET Threshold
2.564
2.630
2.696
V
RESET Threshold Hysteresis (Note 6)
6.3
-
-
mV
V_IN to RESET Delay
RESET/RESET Active Timeout Period (Notes 5,6)
VCC = V_TH to V_TH - 100mV
-
20
-
µs
25
-
-
ms
FAULT
Rising Threshold
% of VOUT
5.0
5.5
6.0
%
Falling Threshold
% of VOUT
-5.0
-5.5
-5.0
%
NOTES:
4. Specifications at -40°C are guaranteed by design/characterization, not production tested.
5. The dropout voltage is defines as V_IN - V_OUT, when V_OUT is 50mV below the value of V_OUT for V_IN = V_OUT + 0.5V.
6. The RESET time is linear with CT at a slope of 2.5ms/nF. Thus, at 10nF (0.01µF) the RESET time is 25ms; at 100nF (0.1µF) the RESET time
would be 250ms.
7. Guaranteed by design, not production tested.
8. LDO1 is guaranteed by design to be within regulation at 2.7V minimum input voltage.
Typical Performance Curves
0.140
0.120
0.100
0.080
0.060
0.040
0.020
0.000
0.00 0.05 0.10 0.15 0.20 0.25 0.30
I_O (Amps)
FIGURE 1. LD02 DROPOUT VOLTAGE
0.100
0.090
0.080
0.070
0.060
0.050
0.040
0.030
0.020
0.010
0.000
0.00
0.05
0.10
0.15
0.30
I_O (Amps)
FIGURE 2. LD03 DROPOUT VOLTAGE
5