ISL59311_14 Datasheet, PDF (5/14 Pages) Intersil Corporation – Differential Video Amplifier with Common Mode Sync Encoder and Serial Digital Interface

ISL59311
Electrical Specifications V_CCA = V_CCD = V_CCS = +5V, GND_A = GND_D = 0V, T_A = +25°C, V_IN = 0V, R_L = 200Ω, unless otherwise
specified. (Continued)
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
PSRR
Rejection of V_CCA
Digital Transceiver Block Electrical Characteristics
60
75
dB
TRANSMITTER DC CHARACTERSTICS
S_OUT± Differential Output Voltage
No load
R_L = 100Ω (Figure 1A)
Change in Magnitude of Driver Differential
S_OUT± for Complementary Output States
R_L = 100Ω (Figure 1A)
|(S_OUT+) - (S_OUT-)|
S_OUT± Common-Mode Voltage (deviation
from V_CCD/2)
R_L = 100Ω (Figure 1A)
S_OUT± Short Circuit Current
Driving high, output tied to GND
Driving low, output tied to V_CCD
S_OUT± Leakage Current
S_OUT (Transmit = GND)
TRANSMITTER SWITCHING CHARACTERISTICS
V_CCD
V
3.0
3.3
V
.08
0.2
V
-0.1
±0.06
+0.1
V
95
110
mA
95
110
mA
±2
±100
nA
Maximum Data Rate
Differential Propagation Delay
Differential Output Skew
Output Enable Time
Output Disable Time
Disabled Output Leakage
R_L = 100Ω, (Figure 1A)
t_PLH (Figure 2, R_DIFF = 100Ω)
t_PHL (Figure 2, R_DIFF = 100Ω)
|t_PLH – t_PHL| (Figure 2, R_DIFF = 100Ω)
t_PZH: Driver Enable to Output High
(Figure 3, I_SINK = 1mA, I_SOURCE = off)
t_PZL: Driver Enable to Output Low
(Figure 3, I_SINK = off, I_SOURCE = 1mA)
t_PHZ: Output High to Output Disabled
(Figure 3, I_SINK = 25mA, I_SOURCE = off)
t_PLZ: Output Low to Output Disabled
(Figure 3, I_SINK = off, I_SOURCE = 25mA)
50
Mbps
6
10
ns
6
10
ns
2
4
ns
4
20
ns
6
20
ns
28
35
ns
28
35
ns
±2
±100
nA
RECEIVER DC CHARACTERISTICS
S_IN± Input Hysteresis
V_CM = 2.5V
S_IN± Input Range
S_IN± Input Resistance; Each Input to GND
RECEIVER SWITCHING CHARACTERISTICS
2
30
50
mV
GND - 0.5
V_CC + 0.5
V
2.5
3.0
3.5
kΩ
Maximum Data Rate
Driven with 100mV differential signal
50
(Figure 4, Note 4)
Mbps
Receiver Input to Output Propagation Delay
Receiver Skew
t_RISE/t_FALL
Receiver Enable to Output High
T_PLH (Figure 4)
T_PHL (Figure 4)
|t_PLH – t_PHL| (Figure 4)
100kΩ II10pF load
4.7
8
ns
5.5
8
ns
0.8
2
ns
2
ns
15
20
ns
Receiver Enable to Output Low
35
42
ns
Receiver High to Hi-Z
15
25
ns
5
FN6372.3
April 25, 2007