ISL5761_15 Datasheet, PDF (5/14 Pages) Intersil Corporation – 10-bit, +3.3V, 130/210+MSPS, High Speed D/A Converter

ISL5761
Electrical Specifications
PARAMETER
AV_DD = DV_DD = +3.3V, V_REF = Internal 1.2V, IOUTFS = 20mA, T_A = 25^oC for All Typical Values (Continued)
T_A = -40^oC TO 85^oC
TEST CONDITIONS
MIN TYP MAX UNITS
Spurious Free Dynamic Range,
SFDR to Nyquist (f_CLK/2)
f_CLK = 210MSPS, f_OUT = 80.8MHz (Notes 4, 7)
-
50
-
dBc
f_CLK = 210MSPS, f_OUT = 40.4MHz (Notes 4, 7, 9)
-
58
-
dBc
f_CLK = 200MSPS, f_OUT = 20.2MHz, T = 25^oC (Notes 4, 7)
58
60
-
dBc
f_CLK = 200MSPS, f_OUT = 20.2MHz, T = -40^oC to 85^oC (Notes 4, 7) 56
-
-
dBc
f_CLK = 130MSPS, f_OUT = 50.5MHz (Notes 4, 7)
-
55
-
dBc
f_CLK = 130MSPS, f_OUT = 40.4MHz (Notes 4, 7)
-
60
-
dBc
f_CLK = 130MSPS, f_OUT = 20.2MHz (Notes 4, 7)
-
68
-
dBc
f_CLK = 130MSPS, f_OUT = 10.1MHz (Notes 4, 7)
-
70
-
dBc
f_CLK = 130MSPS, f_OUT = 5.05MHz, T = 25^oC (Notes 4, 7)
68
75
-
dBc
f_CLK = 130MSPS, f_OUT = 5.05MHz, T = -40^oC to 85^oC (Notes 4, 7) 66
-
-
dBc
f_CLK = 100MSPS, f_OUT = 40.4MHz (Notes 4, 7)
-
58
-
dBc
f_CLK = 80MSPS, f_OUT = 30.3MHz (Notes 4, 7)
-
61
-
dBc
f_CLK = 80MSPS, f_OUT = 20.2MHz (Notes 4, 7)
-
67
-
dBc
f_CLK = 80MSPS, f_OUT = 10.1MHz (Notes 4, 7, 9)
-
69
-
dBc
f_CLK = 80MSPS, f_OUT = 5.05MHz (Notes 4, 7)
-
74
-
dBc
f_CLK = 50MSPS, f_OUT = 20.2MHz (Notes 4, 7)
-
66
-
dBc
f_CLK = 50MSPS, f_OUT = 10.1MHz (Notes 4, 7)
-
72
-
dBc
f_CLK = 50MSPS, f_OUT = 5.05MHz (Notes 4, 7)
-
75
-
dBc
Spurious Free Dynamic Range,
f_CLK = 210MSPS, f_OUT = 28.3MHz to 45.2MHz, 2.1MHz Spacing,
-
63
-
dBc
SFDR in a Window with Eight Tones 50MHz Span (Notes 4, 7, 9)
f_CLK = 130MSPS, f_OUT =17.5MHz to 27.9MHz, 1.3MHz Spacing,
-
66
-
dBc
35MHz Span (Notes 4, 7)
f_CLK = 80MSPS, f_OUT = 10.8MHz to 17.2MHz, 811kHz Spacing,
-
73
-
dBc
15MHz Span (Notes 4, 7)
f_CLK = 50MSPS, f_OUT = 6.7MHz to 10.8MHz, 490kHz Spacing,
10MHz Span (Notes 4, 7)
-
75
-
dBc
Spurious Free Dynamic Range,
f_CLK = 78MSPS, f_OUT = 11MHz, in a 20MHz Window, RBW=30kHz
-
83
-
dBc
SFDR in a Window with EDGE or GSM (Notes 4, 7, 9)
Adjacent Channel Power Ratio,
f_CLK = 76.8MSPS, f_OUT = 19.2MHz, RBW=30kHz (Notes 4, 7, 9)
-
65
-
dB
ACPR with UMTS
VOLTAGE REFERENCE
Internal Reference Voltage, V_FSADJ
Internal Reference Voltage Drift
Pin 18 Voltage with Internal Reference
1.2 1.23
1.3
V
-
40
-
ppm/^oC
Internal Reference Output Current
Reference is not intended to be externally loaded (REFIO pin)
-
0
-
A
Sink/Source Capability
Reference Input Impedance
-
1
-
M
Reference Input Multiplying Bandwidth (Note 7)
-
1.0
-
MHz
DIGITAL INPUTS D9-D0, CLK
Input Logic High Voltage with
3.3V Supply, V_IH
Input Logic Low Voltage with
3.3V Supply, V_IL
Sleep Input Current, I_IH
(Note 3)
(Note 3)
2.3
3.3
-
V
-
0
1.0
V
-25
-
+25
A
5