ISL5627 Datasheet, PDF (5/12 Pages) Intersil Corporation – Dual 8-bit, +3.3V, 260+MSPS, High Speed D/A Converter

ISL5627
Absolute Maximum Ratings
Digital Supply Voltage DV_DD to DGND . . . . . . . . . . . . . . . . . . +3.6V
Analog Supply Voltage AV_DD to AGND . . . . . . . . . . . . . . . . . . +3.6V
Grounds, AGND TO DGND . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
Digital Input Voltages (DATA, CLK, SLEEP) . . . . . . . . DV_DD + 0.3V
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AV_DD + 0.3V
Analog Output Current (I_OUT) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to 85°C
Thermal Information
Thermal Resistance (Typical, Note 1)
θ_JA(°C/W)
LQFP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to 150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θ_JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications AV_DD = DV_DD = +3.3V, V_REF = Internal 1.2V, IOUTFS = 20mA, T_A = 25°C for All Typical Values
PARAMETER
TEST CONDITIONS
T_A = -40°C TO 85°C
MIN TYP MAX
UNITS
SYSTEM PERFORMANCE
Resolution
8
-
-
Bits
Integral Linearity Error, INL
“Best Fit” Straight Line (Note 8)
-0.5 ±0.05 +0.5
LSB
Differential Linearity Error, DNL
(Note 8)
-0.5 ±0.05 +0.5
LSB
Offset Error, I_OS
Offset Drift Coefficient
IOUTA (Note 8)
(Note 8)
-0.006
+0.006 % FSR
-
0.1
-
ppm
FSR/°C
Full Scale Gain Error, FSE
With External Reference (Notes 2, 8)
-3
±0.5
+3 % FSR
With Internal Reference (Notes 2, 8)
-3
±0.5
+3 % FSR
Full Scale Gain Drift
With External Reference (Note 8)
-
±50
-
ppm
FSR/°C
With Internal Reference (Note 8)
-
±100
-
ppm
FSR/°C
Crosstalk
Gain Matching Between Channels
(DC Measurement)
f_CLK = 100MSPS, f_OUT = 10MHz
f_CLK = 100MSPS, f_OUT = 40MHz
f_CLK = 260MSPS, f_OUT = 40.4MHz
As a percentage of Full Scale Range
In dB Full Scale Range
-
-
-
-1.6
-0.14
83
74
73
0.6
0.05
-
-
-
+1.6
+0.14
dB
dB
dB
% FSR
dB FSR
Full Scale Output Current, I_FS
Output Voltage Compliance Range
(Note 3)
2
20
22
mA
-1.0
-
1.25
V
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, f_CLK
Output Rise Time
Full Scale Step
260 300
-
-
1
-
MHz
ns
Output Fall Time
Full Scale Step
-
1
-
ns
Output Capacitance
-
5
-
pF
Output Noise
IOUTFS = 20mA
-
50
-
pA/ √Hz
IOUTFS = 2mA
-
30
-
pA/ √Hz
5