ISL54051_0709 Datasheet, PDF (5/10 Pages) Intersil Corporation – Ultra Low ON-Resistance, Low Voltage, Single Supply, Single SPST Analog Switches

ISL54051, ISL54052
Electrical Specifications - 1.8V Supply
Test Conditions: V+ = +1.8V, GND = 0V, V_INH = 1V, V_INL = 0.4V (Note 4),
Unless Otherwise Specified. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
MIN
MAX
(°C) (Notes 5, 6) TYP (Notes 5, 6) UNITS
DYNAMIC CHARACTERISTICS
Turn-ON Time, t_ON
V+ = 1.8V, V_NO or V_NC = 1.5V, R_L = 50Ω, C_L = 35pF
25
-
68
-
ns
(See Figure 1, Note 8)
Full
-
93
-
ns
Turn-OFF Time, t_OFF
V+ = 1.8V, V_NO or V_NC = 1.5V, R_L = 50Ω, C_L = 35pF
25
-
45
-
ns
(See Figure 1, Note 8)
Full
-
71
-
ns
Charge Injection, Q
V_G = V+/2, R_G = 0Ω, C_L = 1.0nF (See Figure 2)
DIGITAL INPUT CHARACTERISTICS
25
-
18
-
pC
Input Voltage Low, V_INL
Input Voltage High, V_INH
NOTES:
Full
-
Full
1
-
0.4
V
-
-
V
4. V_IN = input voltage to perform proper function.
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Parts are 100% tested at +25°C. Over-temperature limits established by characterization and are not production tested.
7. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range.
8. Limits established by characterization and are not production tested.
Test Circuits and Waveforms
V_INH
LOGIC
INPUT
V_INL
SWITCH
INPUT
V_NX
SWITCH
OUTPUT _0V
50%
t_OFF
V_OUT
90%
t_ON
t_r < 20ns
t_f < 20ns
90%
V+
C
SWITCH
INPUT
LOGIC
INPUT
NO OR NC
IN
GND
COM
V_OUT
R_L
C_L
50Ω 35pF
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 1A. MEASUREMENT POINTS
Repeat test for all switches. C_L includes fixture and stray
capacitance.
V_OUT
=
V(NO _{or NC)}
-----------^R-----^L------------
R_L + r_(ON)
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
C
SWITCH
OUTPUT
V_OUT
ΔV_OUT
R_G
NO OR NC
COM
LOGIC ^ON
V_INH
ON
V_G
INPUT
OFF
V_INL
Q = ΔV_OUT x C_L
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2. CHARGE INJECTION
GND
IN
LOGIC
INPUT
FIGURE 2B. TEST CIRCUIT
V_OUT
C_L
5
FN6459.2
September 25, 2007