ISL43L840 Datasheet, PDF (5/11 Pages) Intersil Corporation – Ultra Low ON-Resistance, Low-Voltage, Single Supply, Dual 4 to 1 Analog Multiplexer

ISL43L840
Test Circuits and Waveforms
V+
LOGIC
INPUT
0V
50%
t_TRANS
t_r < 5ns
t_f < 5ns
VA0, VB0
V_OUT
90%
SWITCH
OUTPUT
0V
10%
0V
t_TRANS
Logic input waveform is inverted for switches that have the opposite
logic sense.
C
V+
LOGIC
INPUT
V+
C
A0,B0
A1-A3
B1-B3
ADD1-0 _GND
COMA
COMB
V_OUT
R_L
50Ω
C_L
35pF
Repeat test for other switches. C_L includes fixture and stray
capacitance.
V_OUT = V(NO _{or NC) R}-----_L----+---^R--_R---^L--₍--_O-----_N----₎
FIGURE 1A. ADDRESS t_TRANS MEASUREMENT POINTS
FIGURE 1B. ADDRESS t_TRANS TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
C
LOGIC ^OFF
INPUT
ON
SWITCH
OUTPUT
V_OUT
V+
OFF
0V
∆V_OUT
R_G
Ax, Bx
COMA
0Ω
COMB
ADDX
V_G
GND
LOGIC
INPUT
Q = ∆V_OUT x C_L
FIGURE 2A. Q MEASUREMENT POINTS
Repeat test for other switches.
FIGURE 2B. Q TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
V_OUT
C_L
1nF
V+
LOGIC
INPUT
0V
t_r < 5ns
t_f < 5ns
C
V+
V+
C
A0-A3
B0-B3
ADD1-0
COMA
COMB
V_OUT
R_L
50Ω
C_L
35pF
SWITCH
OUTPUT
V_OUT
0V
t_BBM
90%
LOGIC
INPUT
GND
Repeat test for other switches. C_L includes fixture and stray
capacitance.
FIGURE 3A. t_BBM MEASUREMENT POINTS
FIGURE 3B. t_BBM TEST CIRCUIT
FIGURE 3. BREAK-BEFORE-MAKE TIME
5
FN6096.1