ISL36411 Datasheet, PDF (5/12 Pages) Intersil Corporation – Quad Lane Extender

ISL36411
Electrical Specifications V_DD = 1.2V, T_A = +25°C, and VIN = 600mV_P-P, unless otherwise noted. (Continued)
PARAMETERS
SYMBOL
CONDITION
MIN TYP MAX UNITS NOTES
Output Return Loss Limit
(Differential)
S_DD22
100MHz to 4.1GHz
4.1MHz to 11.1GHz
Note 7
Note 8
dB
7
dB
8
Output Return Loss Limit
(Common Mode)
S_CC22
100MHz to 2.5GHz
2.5MHz to 11.1GHz
Note 9
-3
dB
9
dB
14
Output Return Loss Limit
S_DC22 100MHz to 11.1GHz
(Com. to Diff. Conversion)
-10
dB
14
Output Residual Jitter
Output Transition Time
Lane-to-Lane Skew
t_r, t_f
10Gbps; Up to 10m 28AWG std twin-
axial cable (~ -27dB @ 5GHz);
1200mV_P-P ≤ VIN ≤ 1600mV_P-P
20% to 80%
0.35
32
50
UI
6, 10,
11
ps
12
ps
14
Propagation Delay
From IN[k] to OUT[k]
500
ps
14
LOS Assert Time
Time to assert Loss-of-Signal indicator
50
when transitioning from active data
mode to line silence mode
µs
13
LOS De-Assert Time
Time to assert Loss-of-Signal indicator
50
when transitioning from line silence
mode to active data mode
µs
13
Data-to-Line Silence
Response Time
K28.5 data pattern at 10Gbps
100
µs
13
Data-to-Line Silence
Response Time
K28.5 data pattern at 10Gbps
100
µs
13
NOTES:
6. After channel loss, differential amplitudes at ISL36411 inputs must meet the input voltage range specified in “Absolute
Maximum Ratings” on page 4.
7. Maximum Reflection Coefficient given by equation SDDXX(dB)= -12 + 2*√(f), with f in GHz. Established by characterization
and not production tested.
8. Maximum Reflection Coefficient given by equation SDDXX(dB)= -6.3+13Log10(f/5.5), with f in GHz. Established by
characterization and not production tested.
9. Reflection Coefficient given by equation SCCXX(dB) < -7 + 1.6*f, with f in GHz. Established by characterization and not
production tested.
10. Output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the transmitted
signal (as measured at the input to the channel). Total jitter (TJ) is DJ_PP + 14.1 x RJ_RMS.
11. Measured using a PRBS 2⁷-1 pattern. Deterministic jitter at the input to the lane extender is due to frequency-dependent,
media-induced loss only.
12. Rise and fall times measured using a 1GHz clock with a 20ps edge rate.
13. For active data mode, cable input amplitude is 300mV_P-P (differential) or greater. For line silence mode, cable input amplitude
is 20mV_P-P (differential) or less. Established by characterization and not production tested.
14. Limits established by characterization and are not production tested.
5
FN6965.1
March 25, 2010