ISL34340 Datasheet, PDF (5/10 Pages) Intersil Corporation – WSVGA 24-Bit Long-Reach Video Serdes with Bidirectional Side-Channel

ISL34340
Electrical Specifications
PARAMETER
Unless otherwise indicated, all data is for: VDD_CDR = VDD_CR = 1.8V, VDD_IO = 3.3V_, VDD_TX = VDD_P =
VDD_AN = 3.3V, T_{A =} +25°C, Ref_Res = 3.16kΩ, High-speed AC-coupling capacitor = 27nF. (Continued)
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
HS Common Mode Serializer-Deserializer
Voltage Difference
ΔV_CM
20
120
mV
HS Differential Output Impedance
HS Output Latency
HS Output Rise and Fall Times
HS Differential Skew
HS Output Random Jitter
HS Output Deterministic Jitter
HIGH SPEED RECEIVER
R_OUT
t_LPD
t_R/t_F
t_SKEW
t_RJ
t_DJ
Part-to-part
20% to 80%
80
100
120
Ω
4
7
10
PCLK
150
ps
<10
ps
13.4
40
ps_rms
ps_P-P
HS Differential Input Voltage
HS Generated Input Common Mode Voltage
HS Differential Input Impedance
HS Maximum Jitter Tolerance
I²C
I²C Clock Rate (on SCL)
I²C Clock Pulse Width (HI or LO)
I²C Clock Low to Data Out Valid
I²C Start/Stop Setup/Hold Time
I²C Data in Setup Time
I²C Data in Hold Time
I²C Data out Hold Time
V_ID
V_ICM
R_IN
F_I2C
150
2.32
mV_P-P
V
80
100
120
Ω
0.52
UI_P-P
100
400
kHz
1.3
µs
0
1
µs
0.6
µs
100
ns
100
ns
100
ms
Pin Descriptions
PIN NUMBER
52 to 63,
2 to 13
22
23
21
26
51
41, 40
24
25
49
PIN NAME
SERIALIZER
RGBA[7:0],
Parallel video data LVCMOS inputs
RGBB[7:0], RGBC[7:0]
HSYNC
Horizontal (line) Sync LVCMOS input
VSYNC
Vertical (frame) Sync LVCMOS input
DATAEN
Video Data Enable LVCMOS input
PCLK_IN
Pixel clock LVCMOS input
PCLK_OUT
Default not used
SERIOP/N
High speed differential serial I/O
HSYNCPOL
CMOS input for HSYNC
1: HSYNC is active low
0: HSYNC is active high
VSYNCPOL
CMOS input for VSYNC
1: VSYNC is active low
0: VSYNC is active high
VIDEO_TX
CMOS input for video flow direction
1: video serializer
0: video deserializer
DESCRIPTION
DESERIALIZER
Parallel video data LVCMOS outputs
Horizontal (line) Sync LVCMOS output
Vertical (frame) Sync LVCMOS output
Video Data Enable LVCMOS output
PLL reference clock LVCMOS input
Recovered clock LVCMOS output
High speed differential serial I/O
5
FN6255.0
March 7, 2008