ISL22349 Datasheet, PDF (5/12 Pages) Intersil Corporation – Quad Digitally Controlled Potentiometers

ISL22349
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
TYP
MIN (NOTE 5) MAX
SERIAL INTERFACE SPECS
V_IL
A2, A1, A0, SHDN, SDA, and SCL
Input Buffer LOW Voltage
-0.3
0.3*V_CC
V_IH
A2, A1, A0, SHDN, SDA, and SCL
Input Buffer HIGH Voltage
0.7*V_CC
V_CC+0.3
Hysteresis SDA and SCL Input Buffer Hysteresis
V_OL
SDA Output Buffer LOW Voltage,
Sinking 4mA
0.05*
V_CC
0
0.4
Cpin A2, A1, A0, SHDN, SDA, and SCL Pin
10
(Note 13) Capacitance
f_SCL
SCL Frequency
400
t_sp
Pulse Width Suppression Time at SDA Any pulse narrower than the max spec is
50
and SCL Inputs
suppressed
t_AA
SCL Falling Edge to SDA Output Data SCL falling edge crossing 30% of V_CC, until
900
Valid
SDA exits the 30% to 70% of V_CC window
t_BUF
Time the Bus Must be Free Before the SDA crossing 70% of V_CC during a STOP
Start of a New Transmission
condition, to SDA crossing 70% of V_CC
during the following START condition
1300
t_LOW
t_HIGH
t_SU:STA
Clock LOW Time
Clock HIGH Time
START Condition Setup Time
t_HD:STA START Condition Hold Time
t_SU:DAT Input Data Setup Time
t_HD:DAT Input Data Hold Time
Measured at the 30% of V_CC crossing
Measured at the 70% of V_CC crossing
SCL rising edge to SDA falling edge; both
crossing 70% of V_CC
From SDA falling edge crossing 30% of V_CC
to SCL falling edge crossing 70% of V_CC
From SDA exiting the 30% to 70% of V_CC
window, to SCL rising edge crossing 30% of
V_CC
From SCL rising edge crossing 70% of V_CC
to SDA entering the 30% to 70% of V_CC
window
1300
600
600
600
100
0
t_SU:STO
t_HD:STO
t_DH
STOP Condition Setup Time
From SCL rising edge crossing 70% of V_CC,
to SDA rising edge crossing 30% of V_CC
STOP Condition Hold Time for Read, From SDA rising edge to SCL falling edge;
or Volatile Only Write
both crossing 70% of V_CC
Output Data Hold Time
From SCL falling edge crossing 30% of V_CC,
until SDA enters the 30% to 70% of V_CC
window
600
1300
0
t_R
SDA and SCL Rise Time
From 30% to 70% of V_CC
20 +
250
0.1 * Cb
t_F
SDA and SCL Fall Time
From 70% to 30% of V_CC
20 +
250
0.1 * Cb
Cb
Capacitive Loading of SDA or SCL Total on-chip and off-chip
10
400
Rpu
SDA and SCL Bus Pull-up Resistor Maximum is determined by t_R and t_F
1
Off-chip
For Cb = 400pF, max is about 2~2.5kΩ
For Cb = 40pF, max is about 15~20kΩ
t_SU:A A2, A1 and A0 Setup Time
Before START condition
600
UNIT
V
V
V
V
pF
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
kΩ
ns
5
FN6331.2
September 15, 2006