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ISL12024IRTCZ Datasheet, PDF (5/24 Pages) Intersil Corporation – Real-Time Clock/Calendar with Embedded Unique ID | |||
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ISL12024IRTCZ
AC Electrical Specifications (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
(Note 12) TYP (Note 12) UNITS NOTES
Cpin SDA and SCL Pin Capacitance
10
pF 9, 11
tWC Non-Volatile Write Cycle Time
tR
SDA and SCL Rise Time
From 30% to 70% of VDD
tF
SDA and SCL Fall Time
From 70% to 30% of VDD
Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip.
12
20
20+0.1xCb
300
20+0.1xCb
300
10
400
ms
10
ns 9, 11
ns 9, 11
pF 9, 11
RPU SDA and SCL Bus Pull-up Resistor Maximum is determined by tR and tF.
1
Off-chip
For Cb = 400pF, max is about 2kΩ~2.5kΩ.
For Cb = 40pF, max is about 15kΩ~20kΩ
kΩ 9, 11
NOTES:
3. IRQ/FOUT Inactive.
4. VIL = VDD x 0.1, VIH = VDD x 0.9, fSCL = 400kHz
5. VDD > VBAT +VBATHYS
6. Bit BSW = 0 (Standard Mode), ATR = 00h, VBAT â¥1.8V
7. Specified at +25°C.
8. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
9. Limits established by characterization and are not production tested.
10. tWC is the minimum cycle time to be allowed for any non-volatile Write by the user (it is the time from valid STOP condition at the end of Write
sequence of a serial interface Write operation) to the end of the self-timed internal non-volatile write cycle.
11. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device specification.
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Timing Diagrams
Bus Timing
SCL
tSU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
tF
tHIGH
tSU:DAT
tHD:STA
tLOW
tR
tHD:DAT
tAA
tDH
tHD:STO
tSU:STO
tBUF
Write Cycle Timing
SCL
SDA
8TH BIT OF LAST BYTE
ACK
tWC
STOP
CONDITION
START
CONDITION
5
FN6749.0
August 8, 2008
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